Intel ® Celeron ® Processor System Bus Signal Groups - Intel CELERON 1.10 GHZ Datasheet

® ®
Intel Celeron Processor up to 1.10 GHz
open drain and should be pulled high to V
current Intel Celeron processors, but compatibility for future Intel Celeron processor products as
well.
The groups and the signals contained within each group are shown in
for descriptions of these signals.
®
Table 3. Intel Celeron
Group Name
AGTL+ Input
AGTL+ Output
AGTL+ I/O
CMOS Input
CMOS Input
CMOS Output
System Bus Clock
APIC Clock
4
APIC I/O
TAP Input
TAP Output
Power/Other
NOTES:
1. See Section 7.0
2. See Section 7.0
3. See Section 7.0
4. These signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V
operation for the FC-PGA/FC-PGA2 packages.
5. V
CC CORE
VID[4:0] and VID[3:0] are described in
V is used to terminate the system bus and generate V
TT
V is system ground.
SS
V is not connected to the Celeron processor. This supply is used for Voltage Transient Tools.
CC 5
SLOTOCC# is described in
BSEL is described in
EMI pins are described in
V is a Pentium
CC L2
processor and may be left as a no-connect for "Intel Celeron processor-only" designs.
6. Only applies to Intel Celeron processors in the S.E.P. Package.
7. Only applies to Intel Celeron processors in the PPGA and FC-PGA/FC-PGA2 packages.
8. The BR0# pin is the only BREQ# signal that is bidirectional. See
9. These signals are specified for 2.5 V operation.
10.BSEL1 is not used in Celeron processors.
11. RESET# must always be terminated to V
provided for this signal on FC-PGA/FC-PGA2 packages.
12.For the FC-PGA/FC-PGA2 packages, this signal is used to control the value of the processor on-die
termination resistance. Refer to the specific platform design guide for the recommended pull-down resistor
value.
13.Only applies to Intel Celeron processors in the FC-PGA/FC-PGA2 packages.
14.S.E.P. Package and FC-PGA/FC-PGA2 packages.
22
®
Processor System Bus Signal Groups
BPRI#, DEFER#, RESET#
PRDY#
A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#
HITM#, LOCK#, REQ[4:0]#,
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#
4
STPCLK#
1,9
PWRGOOD
4 FERR#, IERR#, THERMTRIP#
9
BCLK
9
PICCLK
PICD[1:0]
4 TCK, TDI, TMS, TRST#
4
TDO
7
CPUPRES# , EDGCTRL
5 CC 1.5 7 CC 2.5 7
V , V
6
VID[4:0] , V [7:0]
REF
for information on the PWRGOOD signal.
for information on the SLP# signal.
for information on the THERMTRIP# signal.
is the power supply for the processor core.
Section 7.0.
Section 2.7.2 and
Section 7.0.
®
II processor reserved signal provided to maintain compatibility with the Pentium
. This ensures not only correct operation for
CC CMOS
Signals
11
, RS[2:0]#, TRDY#
3
7 6 7
, EMI , PLL[2:1] , SLOTOCC#
CC L2 5 CC 5 6 CC CMOS 7
, V , V , V , V
7 14 12
, V , V , RTTCTRL
SS TT
Section 2.0.
on the processor substrate.
REF
Section 7.0.
Section 7.0
on the motherboard for PGA packages. On-die termination is not
TT
Table 3. Refer to Section 7.0
8
, D[63:0]#, DBSY#, DRDY#, HIT#,
6
, THERMDP, THERMDN,
CORE DET 7
, V , VID[3:0]
CC CORE
10 13
, BSEL[1:0] , SLEWCTRL
for more information.
2
,
7
,
®
II
Datasheet