Intel Pentium 4 Design Manual page 10

Introduction
Figures
Figure 1.Typical System Configuration ............................................................................. 23
Figure 2. Processor Socket Quadrant Layout ................................................................... 29
Figure 3. Intel
Figure 4. Intel
Figure 5. Desktop Component Placement Example (6-Layer Motherboard) .................... 32
Figure 6. Desktop Component Placement Example (4-Layer Motherboard) .................... 33
Figure 7. Four-Layer Routing Strategy.............................................................................. 35
Figure 8. Six Layer Stack-Up ............................................................................................ 36
Figure 9. Example Stack-Up for 6-Layer ATX Form Factor .............................................. 37
Figure 10. 4-Layer Intel
Chipset Example Stack-Up for µATX Form Factor.................................................... 38
Figure 11. Clocking Architecture Using the CK00............................................................. 40
Figure 12. Processor BCLK Topology............................................................................... 41
Figure 13. Source Shunt Termination ............................................................................... 42
Figure 14. Clock Skew as Measured from Agent to Agent ............................................... 45
Figure 15. Trace Spacing .................................................................................................. 45
Figure 16. BCLK[1:0] Frequency Select for 100 MHz System Bus Operation .................. 46
Figure 17. BCLK [1:0] Frequency Select for 133 MHz System Bus Operation ................. 47
Figure 18. VddIR and 3VMRef Routing............................................................................. 48
Figure 19. Intel
Figure 20. Rambus RDRAM* Device Clock Routing Dimension....................................... 50
Figure 21. Differential Clock Routing ................................................................................ 51
Figure 22. Non-Differential Clock Routing......................................................................... 52
Figure 23. CFM/CFM# Termination - 300/400 MHz Rambus RDRAM* Technology ....... 53
Figure 24. CFM/CFM# Termination - 533 MHz Rambus RDRAM* Technology .............. 53
Figure 25. Rambus DRCG* Impedance Matching Network .............................................. 54
Figure 26. Rambus DRCG* Layout Example.................................................................... 55
Figure 27. 66 MHz / 33 MHz Clock Relationships............................................................. 56
Figure 28. AGP_66 Clock Routing Topology .................................................................... 57
Figure 29. CLK_66 Clock Routing Topology ..................................................................... 57
Figure 30. PCI_33 Clock Routing Topology ...................................................................... 58
Figure 31. CLK_33 Clock Routing Topology ..................................................................... 59
Figure 32. GTLREF Routing.............................................................................................. 63
Figure 33. Processor Topology ......................................................................................... 66
Figure 34. Routing Illustration for FERR# ......................................................................... 72
Figure 35. Routing Illustration for PROCHOT# and THERMTRIP# (Topology 1B) .......... 73
Figure 36. Routing Illustration for A20M#, IGNNE#, LINT[1:0], SLP#, SMI#, and
STPCLK# ................................................................................................................... 73
Figure 37. Routing Illustration for INIT# ............................................................................ 74
Figure 38. Voltage Translation of INIT# ............................................................................ 74
Figure 39. Routing Illustration for PWRGOOD ................................................................. 75
Figure 40. Routing Illustration for VCCIOPLL, VCCA and VSSA...................................... 75
Figure 41. Routing Illustration for BR0# and RESET# ...................................................... 76
Figure 42. Passing Monotonic Rising Edge Voltage Waveform ....................................... 79
Figure 43. Failing Non-monotonic Rising Voltage Waveform ........................................... 79
Figure 44. THERMTRIP# Power Down Circuit.................................................................. 80
Figure 45. Power Sequencing Block Diagram .................................................................. 80
Figure 46: Power-on Sequence Timing Diagram .............................................................. 81
Figure 47. Power-off Sequence Timing Diagram .............................................................. 81
Figure 48. THERMTRIP# Power Down Sequence............................................................ 82
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850/850E Chipset Quadrant Layout ......................................................... 30
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ICH2 Quadrant Layout.............................................................................. 30
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Pentium
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MCH to Rambus DRCG* Routing........................................................... 49
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Intel Pentium 4 Processor / Intel
4 Processor in the 478 Pin Package and Intel
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850 Chipset Family Platform Design Guide
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