Intel Pentium 4 Design Manual page 245

R
Checklist Items
IERR#
IGNNE#
INIT#
LINT[1:0]
LOCK#
MCERR#
PROCHOT#
PWRGOOD
REQ[4:0]#
Reserved
RESET#
RS[2:0]#
RSP#
SKTOCC#
SLP#
® ®
Intel Pentium 4 Processor / Intel
Recommendations
• Leave as a No Connect
• Connect to ICH2.
• No pull-up required.
• Connect to ICH2 and Firmware Hub
(FWH).
• Voltage translation is required for this
signal to meet the input threshold
levels of the FWH.
• Connect to ICH2. LINT[1] connects to
ICH2 NMI and LINT[0] connects to
ICH2 INTR.
• No pull-up required.
• Connect to MCH
• Leave as No Connect
• Terminate to VCC_CPU with a
62 Ω ±5% resistor near the
processor.
• Voltage translation may be required if
this signal is connected to external
logic.
• Terminate to VCC with a 300 Ω ±5%
resistor.
• Connect to ICH2.
• Connect to MCH
• Reserved signals must remain as a
No Connect.
• Terminate to VCC_CPU with a
51 Ω ±5% resistor near the
processor.
• Connect to the MCH.
• Connect to MCH
• Leave as No Connect.
• Connect to glue logic if pin is used.
• Connect to ICH2.
• No pull-up required.
®
850 Chipset Family Platform Design Guide
Schematic Review Checklist
Reason/Impact/Documentation
• Chipset does not support this signal.
• Asynch GTL+ output signal.
• Termination not required.
• Asynch GTL+ input signal.
• Refer to Section 5.4.1.2.
• Termination not required.
• Asynch GTL+ input signal.
• Refer to Section 5.4.1.3.
• Asynch GTL+ Input Signal.
• Refer to Section 5.4.1.2.
• AGTL+ common clock I/O signal
• Chipset does not support this signal.
• AGTL+ common clock I/O signal
• Asynch GTL+ output signal
• Refer to Section 5.4.1.1.
• Asynch GTL+ input signal
• Refer to Section 5.4.1.4.
• AGTL+ source synch I/O signals
•
• AGTL+ common clock input signal
• AGTL+ common clock input signal
• Chipset does not support this signal.
• AGTL+ common clock input signal
• Processor pulls this signal to GND.
System board designers may use this
pin to determine if the processor is
present in the socket.
• Asynch GTL+ input signal
• Refer to Section 5.4.1.2.
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