Intel Pentium 4 Design Manual page 275

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Intel Pentium 4 Processor / Intel
Recommendations
• Connect individual 33 MHz clock signals to
ICH2, FWH, and SIO. Trace length from
CK00 chip to series resistor should be
0–0.5 inches and from series resistor to
receiver should be Z + (4 – 6 inches). Route
singles on a single layer.
• Z = 5 inches to 9 inches
• Connect individual PCI 33 MHz clock
signals to PCI slots. Trace length from
CK00 chip to series resistor should be
0 – 0.5 inches and from series resistor to
receiver should be Z + (2 – 4 inches).
Route signals on a single layer.
• Z = 5 inches to 9 inches
• Connect individual 66 MHz clock signals to
ICH2 and MCH.
• Trace length from CK00 to series resistor
should be 0 – 0.5 inches and from series
resistor to receiver should be
Z + (4 – 5 inches). Route signals on a
single layer.
• Z = 5 inches to 9 inches.
• Connect 66 MHz clock signal to AGP
connector.
• Trace length from the CK00 to series
resistor should be 0 – 0.5 inches and from
series resistor to receiver should be equal to
Z (5 –9 inches). Route signals on a single
layer.
®
850 Chipset Family Platform Design Guide
Layout Review Checklist
Reason/Impact/Documentation
• This recommendation insures setup and
hold times in relation to the other clock
signals are maintained. Clock length routing
relationships, located in Section 4.4.1 of this
document, between clock signals should be
observed.
• Refer to Section 4.4 and Section 4.4.2.1.
• This recommendation insures setup and
hold times in relation to the other clock
signals are maintained. Clock length routing
relationships, located in Section 4.4.1 of this
document, between clock signals should be
observed.
• Refer to Section 4.4 and Section 4.4.2.1.
• This recommendation insures setup and
hold times in relation to the other clock
signals are maintained. Clock length routing
relationships, located in Section 4.4.1 of this
document, between clock signals should be
observed.
• Refer to Section 4.4 and Section 4.4.2.
• This recommendation insures setup and
hold times in relation to the other clock
signals are maintained. Clock length routing
relationships, located in Section 4.4.1 of this
document, between clock signals should be
observed.
• Refer to Section 4.4 and Section 4.4.2.
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