Intel Pentium 4 Design Manual page 13

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Figure 148. Layer 3 Power Delivery Shape (VCC_CPU and VSS) ................................. 207
Figure 149. Layer 4 Power Delivery Shape (VCC_CPU and VSS) ................................. 208
Figure 150. Layer 5 Power Delivery Shape (VSS) .......................................................... 209
Figure 151. Bottom Layer Power Delivery Shape (VCC_CPU)....................................... 210
Figure 152. Alternating VCC_CPU/VSS Capacitor Placement ....................................... 211
Figure 153. Top Layer Power Delivery Shape (VCC_CPU) ............................................ 212
Figure 154. Layer 2 Power Delivery Shape (VSS) .......................................................... 213
Figure 155. Layer 3 Power Delivery Shape (VSS) .......................................................... 213
Figure 156. Bottom Layer Power Delivery Shape (VCC_CPU)....................................... 214
Figure 157. Top Layer Power Delivery Shape (VCC_CPU) ............................................ 215
Figure 158. Layer 2 Power Delivery Shape (Vss) ........................................................... 215
Figure 159. Layer 3 Power Delivery Shape (Vss) ........................................................... 216
Figure 160. Bottom Layer Power Delivery Shape (VCC_CPU)....................................... 216
Figure 161. Shared Power and Ground Vias .................................................................. 217
Figure 162. Routing of VR Feedback Signal ................................................................... 218
Figure 163. Shared Power and Ground Vias .................................................................. 219
Figure 164. Routing of VR Feedback Signal ................................................................... 220
Figure 165. Example Circuit That Can Be Used As a Thermal Monitor.......................... 222
Figure 166. Detailed Power Distribution Model for Processor with Voltage Regulator on
System Board........................................................................................................... 223
Figure 167. Detailed Power Distribution Model for Processor with Voltage Regulator on
System Board........................................................................................................... 224
Figure 168. Typical VCCIOPLL, VCCA and VSSA Power Distribution ........................... 225
Figure 169. Filter Recommendation................................................................................ 226
Figure 170. Example Component Placement for PLL Filter............................................ 227
Figure 171. Global System Power States and Transition................................................ 230
Figure 172. Inductor-Capacitor Filter Circuit ................................................................... 231
Figure 173. Ferrite Bead Filter Circuit ............................................................................. 232
Figure 174. Customer Reference Board Layout Example .............................................. 233
Figure 175. Customer Reference Board Layout Example (Bottom - Layer 6)................ 233
Figure 176. Customer Reference Board Layout Example (Signal 2 - Layer 4) .............. 234
Figure 177. 1.8 V and 2.5 V Power Sequence (Schottky Diode) .................................... 234
Figure 178. Desired Mode of Power Sequencing............................................................ 235
Figure 179. Optional Mode of Power Sequencing........................................................... 235
Figure 180. V5REF Sequencing Circuit .......................................................................... 236
Figure 181. CPU/CK00 Sequencing Circuit .................................................................... 237
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Intel Pentium 4 Processor / Intel
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850 Chipset Family Platform Design Guide
Introduction
13