Intel Pentium 4 Design Manual page 256

Schematic Review Checklist
Checklist Items
SA Pins
SIN & SOUT
SWE (A57)
RESET
V
DD
V
CMOS
256
Recommendations
• Should be connected to VCC3_3 or
GND to set the SMBus address for
that RIMM* modules EEPROM.
• If the SMBus is tied to 3.3V
either:
 Provide proper isolation on SCL
/SDA and pull the HIGH SA pins to
3.3 V
OR
 Tie the HIGH SA pins to 3.3V
Should be daisy-chained between
RIMM connectors:
• MCH SIO pin connects to 1
connector SIN (B36)
• SOUT (A36) on 1
nd
connects to 2
(B36)
• A 2.2 k Ω –10 k Ω terminating resistor,
tied to GND, is required on the last
RIMM connector's SOUT pin.
• If an OEM needs to write to the SPD
devices, it is recommended that this
signal be tied to a GPO pin from
either the ICH2 or the SIO.
• If an OEM does not need to write to
the SPD devices, it is recommended
that this signal be tied to 3.3 V via a
weak pull-up resistor (4.7 k Ω ).
• For the 168-pin RIMM connector, this
is a reserved pin.
• This is connected to 2.5 V (or 2.5V
• It is REQUIRED that the voltage
regulator to the RDRAM* devices
(2.5 V RDRAM device Core) is turned
OFF in S5. This can be
accomplished by connecting the
SLP_S5# signal to the 2.5 V RDRAM
Core voltage regulator.
• PC600/800/1066:
• This is connected to 1.8 V for
RDRAM technology
• V must be OFF in S5.
CMOS
• V can be generated with a
CMOS
voltage divider consisting of a 36 Ω
pull-up resistor to VCC2_5 and 100 Ω
resistor to GND.
® ®
Intel Pentium 4 Processor / Intel
• This sets the SMBus address. Each
device on the SMBus must have an
address to distinguish it from another
device of the same type. That is,
, then
each RIMM* module EEPROM must
SB
be strapped to a different address or
they will all respond on an access.
• Refer to the Rambus datasheets at
http://www.rambus.com
.
SB
• Refer to Section 6.1.6.
• Refer to the Rambus datasheets at
st
http://www.rambus.com
RIMM
st
RIMM connector
RIMM connector SIN
• If SWE = 1, write protected.
• If SWE = 0, not write protected.
• These signals must be driven; do not
leave floating.
• Refer to the RAMBUS datasheets at
http://www.rambus.com
• The connector pad is reserved for
future use for the 168-pin RIMM
connector.
• Refer to the RAMBUS datasheets at
http://www.rambus.com
) • It supplies the core voltage for the
SB
RDRAM* technology and interface
logic.
• S5 is a suspend state and power is
removed from some components on
the motherboard. Therefore, V
should be off while in suspend state.
• Refer to Section 6.1.5.
®
850 Chipset Family Platform Design Guide
R
Reason/Impact
CMOS