System Management Feature Specifications; System Management Bus; System Management Bus Interface; System Management Interface Signals - Intel Itanium 2 Processor Datasheet

2 processor 1.66 ghz with 9 mb l3 cache / 1.66 ghz with 6 mb l3 cache / 1.6 ghz with 9 mb l3 cache / 1.6 ghz with 6 mb l3 cache/ 1.5 ghz with 6 mb l3 cache / 1.5 ghz with 4 mb l3 cache / 1.4 ghz with 4 mb l3 cache / 1.3 ghz with 3 mb l3 cache / 1.0 ghz wi
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6
System Management Feature
Specifications
The Itanium 2 processor includes a system management bus (SMBus) interface. This chapter
describes the features of the SMBus and SMBus components.
6.1

System Management Bus

6.1.1

System Management Bus Interface

The Itanium 2 processor includes an Itanium processor family SMBus interface which allows
access to several processor features. The system management components on the processor include
two memory components (EEPROMs) and a thermal sensing device (digital thermometer). The
processor information EEPROM (PIROM) is programmed by Intel with manufacturing and feature
information specific to the Itanium 2 processor. This information is permanently write-protected.
Section 6.2
available for other data at the system vendor's discretion. The thermal sensor can be used in
conjunction with the information in the PIROM and/or the Scratch EEPROM for system thermal
monitoring and management. The thermal sensing device on the processor provides an accurate
means of acquiring an indicator of the junction temperature of the processor core die. The thermal
sensing device is connected to the anode and cathode of the Itanium 2 processor on-die thermal
diode. SMBus implementation on the Itanium 2 processor uses the clock and data signals as
defined by SMBus specifications.
6.1.2

System Management Interface Signals

Table 6-1
used by the system to access the system management components via the SMBus.
Table 6-1. System Management Interface Signal Descriptions
Signal Name
3.3V
SMA[2:0]
SMSC
SMSD
SMWP
THRMALERT#
Figure 6-1
how the various system management components are connected to the SMBus. The reference to
the System Board at the lower left corner of
for multiple Itanium 2 processors can be realized with resistor stuffing options.
Datasheet
provides detail on the PIROM. The other EEPROM is a scratch EEPROM that is
lists the system management interface signals and their descriptions. These signals are
Pin Count
1
3
1
1
1
1
shows the logical schematics of SMBus circuitry on the Itanium 2 processor and shows
Description
Voltage supply for EEPROMs and thermal sensor.
Address select passed through from socket.
System management bus clock.
System management serial address/data bus.
Scratch EEPROM write protect.
Temperature alert from the thermal sensor.
Figure 6-1
shows how SMBus address configuration
79

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