Intel Pentium 4 Design Manual page 11

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Figure 49. Voltage Divider Network for Reference Voltage Generation............................ 82
Figure 50. Pull-Down Circuit.............................................................................................. 83
Figure 51. Example Intel
Figure 52. Customer Reference Platform System Bus Routing - Top Layer ................... 85
Figure 53, Customer Reference Platform System Bus Routing - Bottom Layer .............. 86
Figure 54. Processor Power Delivery on Layer 2 .............................................................. 87
Figure 55. Processor Power Delivery on Layer 4 .............................................................. 88
Figure 56. Intel
Figure 57. Example Direct Rambus Channel Routing ...................................................... 92
Figure 58. RSL Routing Diagram Showing Ground Isolation Traces with VIA Around RSL
Signals ....................................................................................................................... 93
Figure 59. Direct Rambus Channel Trace Length Matching Example.............................. 94
Figure 60. "Dummy" vs. "Real" Vias.................................................................................. 96
Figure 61. RSL and Clocking Signal Layer Alteration ....................................................... 98
Figure 62. Top Layer CTAB with RSL Signal Routed on the Same Layer (Ceff = 0.8 pF)100
Figure 63. Bottom Layer CTAB with RSL Signal Routed on the Same Layer (Ceff =
1.35 pF).................................................................................................................... 101
Figure 64. Bottom Layer CTABs Split Across the Top and Bottom Layer to Achieve an
Effect Ceff ~1.35 pF................................................................................................. 101
Figure 65. Direct Rambus RDRAM* Device Termination (Discrete Resistors Are
Recommended) ....................................................................................................... 102
Figure 66. Direct Rambus RDRAM* Device Termination Example ................................ 103
Figure 67. RAMREF Generation Example Circuit for 300/400 MHz Rambus RDRAM*
Technology............................................................................................................... 104
Figure 68. RAMREF Generation Example Circuit for 533 MHz Rambus RDRAM*
Technology............................................................................................................... 104
Figure 69. High-Speed CMOS RC Termination .............................................................. 105
Figure 70. SIO Routing.................................................................................................... 106
Figure 71. Rambus RDRAM* Device CMOS Shunt Transistor....................................... 108
Figure 72. Rambus RIMM Connector Placement ........................................................... 110
Figure 73. Rambus Technology Intel
Figure 74. Rambus Technology Intel
Figure 75. AGP 2X/4X Routing Example for Interfaces < 6 Inches ................................ 115
Figure 76. AGP I/O Decoupling Example with a VSS Flood to Improve Power Delivery to
the Intel
Figure 77. AGP 2.0 V
Figure 78. AGP Left Handed Retention Mechanism Drawing......................................... 122
Figure 79. AGP Left Handed Retention Mechanism Keep-out Information .................... 123
Figure 80. Example AGP Routing (Top Layer)................................................................ 124
Figure 81. Example AGP Routing (Bottom Layer) .......................................................... 125
Figure 82. Example VDDQ Plane on Layer 2.................................................................. 126
Figure 83. 8-Bit Hub Interface Routing Example............................................................. 127
Figure 84. 8-Bit Hub Interface with a Shared Reference Divider Circuit (Normal Mode) 129
Figure 85. 8-Bit Hub Interface with Locally Generated Reference Divider Circuits......... 129
Figure 86. Example Hub Interface Breakout / 1.8 V MCH Fingers ................................. 131
Figure 87. Combination Host-Side/Device-Side IDE Cable Detection ............................ 135
Figure 88. Device-Side IDE Cable Detection .................................................................. 136
Figure 89. Connection Requirements for Primary IDE Connector .................................. 137
Figure 90. Connection Requirements for Secondary IDE Connector ............................. 138
Figure 91. CNR Interface ................................................................................................ 139
Figure 92. Intel
Figure 93. Audio Codec................................................................................................... 141
Figure 94. Modem Codec................................................................................................ 141
Figure 95. Audio/Modem Codec...................................................................................... 141
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Intel Pentium 4 Processor / Intel
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MCH Decoupling Guidelines for Chipset ................................. 84
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MCH Direct Rambus Channel Routing Example.................................... 90
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MCH ......................................................................................................... 117
Generation and Distribution for 1.5 V Cards ........................... 119
REF
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ICH2 AC'97 - Codec Connection.......................................................... 140
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850 Chipset Family Platform Design Guide
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MCH Breakout (Top Layer) ................................ 111
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MCH Breakout (Bottom Layer) ........................... 112
Introduction
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