Intel Pentium 4 Design Manual page 12

Introduction
Figure 96. Modem Codecs .............................................................................................. 142
Figure 97. Audio and Modem Codecs............................................................................. 142
Figure 98. Audio Codecs................................................................................................. 143
Figure 99. Audio and Audio/Modem Codecs................................................................... 143
Figure 100. CDC_DN_ENAB# Support Circuitry for a Single Codec Motherboard......... 145
Figure 101. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade ....... 146
Figure 102. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
One-Codec on CNR................................................................................................. 146
Figure 103. CDC_DN_ENAB# Support for Two-Codecs on Motherboard /
Two-Codecs on CNR ............................................................................................... 147
Figure 104. USB Data Signals ........................................................................................ 149
Figure 105. SMBUS/SMLink Interface ............................................................................ 150
Figure 106. Unified VCC_Suspend Architecture ............................................................. 152
Figure 107. Unified VCC_Core Architecture ................................................................... 152
Figure 108. Mixed VCC_Suspend/VCC_Core Architecture ............................................ 153
Figure 109. PCI Bus Layout Example ............................................................................. 153
Figure 110. Example PCI Power Planes on Layer 2 ....................................................... 154
Figure 111. Example PCI Routing on Layer 1................................................................. 155
Figure 112. Example PCI Routing on Layer 4................................................................. 156
Figure 113. External Circuitry for the Intel
Figure 114. Diode Circuit to Connect RTC External Battery ........................................... 159
Figure 115. RTCRST External Circuit for the Intel
Figure 116. RTC Power-Well Isolation Control ............................................................... 161
Figure 117. Intel
Figure 118. Single Solution Interconnect ........................................................................ 164
Figure 119. LOM/CNR Interconnect................................................................................ 165
Figure 120. LAN_CLK Routing Example......................................................................... 166
Figure 121. Trace Routing............................................................................................... 168
Figure 122. Ground Plane Separation............................................................................. 169
Figure 123. Intel
Figure 124. Critical Dimensions for Component Placement ........................................... 174
Figure 125. Intel
Figure 126. Critical Dimensions for Component Placement ........................................... 177
Figure 127. Termination Plane ........................................................................................ 179
Figure 128. Intel
Figure 129. Dual Footprint LAN Connect Interface ......................................................... 181
Figure 130. Dual Footprint Analog Interface ................................................................... 181
Figure 131. Example Intel
Figure 132. Example Intel
Figure 133. FWH VPP Isolation Circuitry ........................................................................ 185
Figure 134. SPKR Circuit ................................................................................................ 187
Figure 135. Example Power-On 3.3 V / 1.8 V Sequencing Circuit .................................. 188
Figure 136. Example PCI IRQ Routing ........................................................................... 189
Figure 137. RM Keepout Drawing 1 ................................................................................ 192
Figure 138. RM Keepout Drawing 2 ................................................................................ 193
Figure 139. Intel
Figure 140. FMB1 VR Component Placement................................................................ 198
Figure 141. Four-Phase VR Component Placement....................................................... 199
Figure 142. Three-Phase VR Component Placement..................................................... 199
Figure 143. Decoupling Placement ................................................................................. 201
Figure 144. Four-Phase Decoupling Placement ............................................................. 203
Figure 145. Three-Phase Decoupling Placement ........................................................... 204
Figure 146. Top Layer Power Delivery Shape (VCC_CPU) ............................................ 205
Figure 147. Layer 2 Power Delivery Shape (VSS) .......................................................... 206
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ICH2 / LAN Connect Section .............................................................. 163
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82562 EH Termination........................................................................ 173
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82562ET/ 82562EM Termination........................................................ 176
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82562ET/EM Disable Circuit .............................................................. 180
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ICH2 Top Layer Breakout Using Standard Size Vias .......... 183
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ICH2 Bottom layer Breakout Using Standard Size Vias ...... 184
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MCH Keepouts and RM Hole Locations............................................. 194
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Intel Pentium 4 Processor / Intel
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ICH2 RTC ................................................... 157
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ICH2 RTC....................................... 160
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850 Chipset Family Platform Design Guide
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