Intel Pentium 4 Design Manual page 8

Introduction
12 Power Distribution Guidelines ......................................................................................... 229
12.1 Definitions ........................................................................................................... 229
12.2 Power Management ........................................................................................... 229
12.2.1
12.2.2
12.3 1.8 V RAC Isolation Solution .............................................................................. 231
12.4 Vterm/Vdd Power Sequencing Requirement...................................................... 234
12.5 Intel
12.6 Intel
12.7 CPU / CK00 Power Sequencing Requirement ................................................... 237
13 Debug Port Routing Guidelines....................................................................................... 239
14 Debug Tools Specifications............................................................................................. 241
14.1 Logic Analyzer Interface (LAI) ............................................................................ 241
14.1.1
14.1.2
15 Schematic Review Checklist ........................................................................................... 243
15.1 Processor Checklist (All Signals)........................................................................ 243
15.2 CK00 Clock Generator Checklist........................................................................ 248
15.3 Direct Rambus Clock Generator (DRCG1 and DRCG2) Checklist .................... 249
15.4 Intel
15.5 AGP Checklist .................................................................................................... 253
15.6 Rambus RIMM* Connector Checklist................................................................. 255
15.7 Intel
15.7.1
15.7.2
15.7.3
15.7.4
15.7.5
15.7.6
15.7.7
15.7.8
15.7.9
15.7.10 Processor Signals ............................................................................... 263
15.7.11 System Management .......................................................................... 264
15.7.12 RTC
15.7.13 Intel
15.7.14 Miscellaneous Signals......................................................................... 265
15.7.15 Power
15.7.16 IDE Interface ....................................................................................... 267
16 Layout Review Checklist ................................................................................................. 269
16.1 Processor and System Bus ................................................................................ 269
16.1.1
16.1.2
16.1.3
16.1.4
16.1.5
16.1.6
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ACPI Hardware Model ........................................................................ 230
Thermal Design Power ....................................................................... 230
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850 Chipset Power Sequencing Requirements ........................................ 235
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ICH2 V5REF and Vcc3.3 Sequencing Requirement................................. 236
Mechanical Considerations ................................................................. 241
Electrical Considerations..................................................................... 241
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850 Chipset Checklist ............................................................................... 251
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ICH2 Checklist .......................................................................................... 259
PCI Interface ....................................................................................... 259
Hub Interface ...................................................................................... 260
LAN* Interface..................................................................................... 260
EEPROM Interface ............................................................................. 260
FWH/LPC Interface............................................................................. 261
Interrupt Interface................................................................................ 261
GPIO ................................................................................................... 262
USB..................................................................................................... 263
Power Management ............................................................................ 263
........................................................................................... 264
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AC'97......................................................................................... 265
........................................................................................... 266
AGTL+ Signals.................................................................................... 269
Asynchronous GTL+ and Other Signals ............................................. 271
Processor Keep-Out Zones ................................................................ 271
Processor Decoupling......................................................................... 272
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Intel 82850 MCH Decoupling ............................................................ 272
AGTL+ ( V HDVREF [3:0], HAVREF [1:0] and CCVREF).............. 273
REF
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Intel Pentium 4 Processor / Intel
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850 Chipset Family Platform Design Guide
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