Intel Pentium 4 Design Manual page 270

Layout Review Checklist
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270
Recommendations
• Address signal (A[35:3]# and REQ[4:0]#)
length should be 2 inches – 10 inches pin-
to-pin. Address signals of the same source
synchronous group should be routed to the
same pad-to-pad length ±200 mils. Length
must be added to the motherboard to
compensate for package length differences.
• ADSTB[1:0]# length should be 2 inches –
10 inches pin-to-pin. Address signals of the
same source synchronous group should be
routed to the same pad-to-pad length
±200 mils. Length must be added to the
motherboard to compensate for package
length differences.
All common clock AGTL+ signals (See below)
routed 6 inches – 10 inches (pin-to-pin). No
length compensation is necessary.
BPRI# DEFER#
RS[2:0]# RSP#
AP[1:0]# ADS#
BNR# BPM[5:0]#
DBSY# DP[3:0]#
HIT# HITM#
MCERR#
• All signals impedance's should equal
50 Ω ±15%
® ®
Intel Pentium 4 Processor / Intel
Reason/Impact/Documentation
• The length compensation will result in
minimizing the source synchronous skew
that exists on the system bus. Without trace
matching and length compensation flight
times between the data signals and the
strobes will result in inequity between the
setup and hold times.
• Refer to Chapter 2.
• The impact of this routing recommendation
causes the strobe to be received closer to
the center of the data pulse, which results in
reasonably comparable setup and hold
times.
• Refer to Chapter 2.
• Refer to Chapter 2.
RESET#
TRDY#
BINIT#
BR0#
DRDY#
LOCK#
• Refer to Chapter 2.
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850 Chipset Family Platform Design Guide
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