Intel Pentium 4 Design Manual page 5

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6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.2 Rambus Technology Routing Guidelines - Four-Layer Motherboard ................. 110
6.2.1
7 AGP Interface Routing .................................................................................................... 113
7.1 AGP Routing Guidelines..................................................................................... 114
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.2 AGP Universal Retention Mechanism (RM) ....................................................... 121
7.3 AGP Routing Guidelines - Four-Layer Motherboard........................................... 124
8 Hub Interface Routing ..................................................................................................... 127
8.1 Hub Interface Routing Guidelines....................................................................... 127
8.2 8-Bit Hub Interface Routing Guidelines .............................................................. 128
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3 Hub Interface Routing Guidelines - Four-Layer Motherboard ............................ 131
9 I/O Controller Hub 2 ........................................................................................................ 133
9.1 This Chapter Provides Information on the Intel
(ICH2) IDE Interface ........................................................................................... 133
9.1.1
9.1.2
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Intel Pentium 4 Processor / Intel
6.1.2.3 Differential Clock Compensation ......................................... 96
6.1.2.3.1 Non-Differentially Routed Clocks - 533 MHz
Rambus RDRAM* Technology ............................ 97
6.1.2.4 Signal Layer Alternation for Rambus RIMM Connector Pin
Compensation ..................................................................... 98
6.1.2.5 Rambus RIMM Connector Impedance Compensation........ 98
RSL Signal Termination ...................................................................... 102
Rambus RDRAM* Device Reference Voltage .................................... 104
High-Speed CMOS Routing ................................................................ 105
SIO Routing......................................................................................... 105
Suspend-to-RAM Shunt Transistor ..................................................... 107
Rambus RDRAM* Device Channel Margin Improvement .................. 108
533 MHz (PC1066) Rambus RIMM Module Thermal Consideration .. 109
Optimized Rambus RDRAM* Device Routing Rules for a Four-Layer
Motherboard Design............................................................................ 112
1X Timing Domain Signal Routing Guidelines .................................... 114
2X/4X Timing Domain Signal Routing Guidelines............................... 114
7.1.2.1 Trace Lengths Less Than 6 Inches ................................... 114
7.1.2.2 Trace Lengths Greater Than 6 Inches and Less Than 7.25
Inches ................................................................................ 115
AGP Interfaces Trace Length Summary............................................. 116
I/O Decoupling Guidelines .................................................................. 117
Signal Power/Ground Referencing Recommendations ...................... 118
VDDQ and TYPEDET# ....................................................................... 118
V Generation .................................................................................. 118
REF
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Intel MCH AGP Interface Buffer Compensation................................ 119
AGP Pull-ups/Pull-down on AGP Signals ........................................... 119
AGP Signal Voltage Tolerance List..................................................... 121
AGP Connector ................................................................................... 121
8-Bit Hub Interface Data Signals......................................................... 128
8-Bit Hub Interface Strobe Signals...................................................... 128
8-Bit Hub Interface HIREF Generation/Distribution ............................ 128
8-Bit Hub Interface Compensation...................................................... 130
8-Bit Hub Interface Decoupling Guidelines ......................................... 130
IDE Cable............................................................................................ 133
Cable Detection for Ultra ATA/66 and Ultra ATA/100 ......................... 134
9.1.2.1 Combination Host-Side/Device-Side Cable Detection....... 135
9.1.2.2 Device-Side Cable Detection............................................. 136
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850 Chipset Family Platform Design Guide
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82801BA I/O Controller Hub 2
Introduction
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