Table 2-6 Notes On The Feedback Bits - Siemens SIMATIC ET 200S Operating Instructions Manual

Notes on the Feedback Bits
Table 2-6 Notes on the Feedback Bits
Feedback bits Notes
ERR_24V Short circuit of the encoder supply
The error bit must be acknowledged by the EXTF_ACK control bit (see figure below)
Diagnostic message if assigned.
ERR_DO1 Short circuit/wire break/overtemperature due to overload at output DO1
The error bit must be acknowledged by the EXTF_ACK control bit (see figure below)
Diagnostic message if assigned.
ERR_LOAD Load function error (see figure below)
The LOAD_VAL, LOAD_PREPARE, CMP_VAL1, CMP_VAL2, and C_DOPARAM bits cannot be set
simultaneously during transfer. This results in setting the ERR_LOAD status bit, similar to loading an
incorrect value (which is not accepted).
ERR_PARA Parameter assignment error ERR_PARA
RES_STS_A Resetting of the status bits active (see figure below)
STS_C_DN Down direction status
STS_C_UP Up direction status
STS_CMP1 Comparator 1 status
The STS_CMP1 status bit indicates that the output is or was switched on. It must be acknowledged
with the RES_STS control bit. If the status bit is acknowledged when the output is still switched on,
the bit is set again immediately. This bit is also set if the SET_DO1 control bit is used when DO1 is
not enabled.
STS_CMP2 Comparator 2 status
The STS_CMP2 status bit indicates that the output is or was switched on. It must be acknowledged
with the RES_STS control bit. If the status bit is acknowledged when the output is still switched on,
the bit is set again immediately. This bit is also set if the SET_DO2 control bit is used when DO2 is
not enabled.
STS_DI DI status
The status of the DI is indicated in all modes with the STS_DI bit in the feedback interface.
STS_DO1 DO1 status
The STS_DO1 status bit indicates the status of the DO1 digital output.
STS_DO2 DO2 status
The STS_DO2 status bit indicates the status of the virtual DO2 digital output.
STS_GATE Internal gate status: Counting
STS_LOAD Load function running (see figure below)
STS_ND Zero-crossing in the count range when counting without a main counting direction. The bit must be
reset by the RES_STS control bit.
STS_OFLW High counting limit violated
STS_UFLW Low counting limit violated
Both bits must be reset.
STS_SYN Synchronization status
After successful synchronization, the STS_SYN bit is set. It must be reset by the RES_STS control
bit.
Technological Functions
Operating Instructions, 02/2007, A5E00124867-05
1Count24V/100kHz
2.6 Count Modes
49