Table of Contents
Advertisement
S5-115U Manual
Evaluating the interrupt request in OB2:
STL OB2
L
PY
9
T
IB
9
A
I
9.0
R
Q
0.0
A
I
9.1
R
Q
0.1
L
QB 0
T
PY 0
BE
Updating the LED statuses in the cyclic program:
STL OB1
:
L
PY
8
T
IB
8
A
I
8.0
=
Q
1.0
A
I
8.1
=
Q
1.1
:
BE
Estimating the interrupt response time
(Prerequisite: no interrupts have been disabled with "IA")
The response time (i.e. the time between energizing the limit switch and switching off the
drive) can be estimated as follows:
Signal delay of the 434-7 DI (approx. 1 ms)
+
Response time of the CPU (see Section 9.2)
+
Execution time of OB2 (=sum of all operation execution times)
=
Total response time
EWA 4NEB 811 6130-02b
Acknowledge interrupt by loading the "mod. addr. +1"
byte; Transfer to PII
Scan: Did limit switch 1 trigger the interrupt?
If yes, reset output Q 0.0 (switch off drive 1)
Scan: Did limit switch 2 trigger the interrupt?
If yes, reset output Q 0.1 (switch off drive 2)
Transfer updated output byte QB 0 direct to the output
module (direct I/O access to minimize response time!)
Load the status of the inputs (low byte)
Transfer low byte to PII
Transfer the status of limit switch 1 to the LED
Transfer the status of limit switch 2 to the LED
Interrupt Processing
Meaning
Meaning
9-9
Advertisement
Table of Contents
