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STEP 5 Operations
Flip-Flop for a Latching Signal Output
A "1" at input I 2.7 sets flip-flop Q 3.5 (signal state "1"). If
the signal state at input I 2.7 changes to "0", the state of
output Q 3.5 is maintained, i.e., the signal is latched.
A "1" at input I 1.4 resets the flip-flop (signal state "0").
When the "SET" signal (input I 2.7) and the "RESET" signal
(input I 1.4) are applied at the same time, the scanning
operation that was programmed last (in this case A I 1.4) is
in effect during processing of the rest of the program.
In this example, resetting output Q 3.5 has priority.
STL
Q
I
2.7
S
Q
3.5
Q
I
1.4
R
Q
3.5
NOP 0
*
*
NOP 0
"NOP 0" is necessary if the program is to be represented in LAD or CSF form on the PG 635, PG 670, PG 675U,
PG 685, or PG 695 programmers. During programming in LAD and CSF, such "NOP 0" operations are allotted
automatically.
8-8
Example
CSF
Q 3.5
I 2.7
S
R Q
I 1.4
S5-115U Manual
Circuit Diagram
I 1.4
I 2.7
Q 3.5
LAD
Q 3.5
I 2.7
S
I 1.4
R Q
EWA 4NEB 811 6130-02b
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