Test Section 3 - HP Series 37 Reference Manual

Test Descriptions
Step 13. Memory Configuration -- This step determines the size of memory by reading a location in each
consecutive bank until a Memory Bounds Violation occurs. This information is displayed by the
following message:
Detected XX banks of memory on Y boards using ZZZK Rams.
Where: XX" 1-32 (indicating the number of banks)
y" 1/2
ZZZ" 64/256
If no valid last bank number is found, the following error message is displayed:
last Bank No. Invalid
If a Memory Bounds Violation is not detected, the following error message is displayed:
Memory Bounds Violation not detected - default ending bank
=
3.
This step does NOT have the Loop on Error option.
Step 14. Clear Memory Status -- This step reads the memory status of I or 2 boards to clear the error
syndrome code. It does NOT have the Loop on Error option.
3.2 TEST SECTION 2
rGDAC Test
This section performs a simple pattern test on all memory boards present. It then checks the Error
Detection and Correction Circuit (EDAC) to ensure that the board will function correctly with single-bit
errors present.
Step 21. Simple Pattern Test -- This step does a simple pattern test before beginning the EDAC test to
detect faulty RAMs. Since the EDAC facility cannot be shut off, this is the only way to ensure
that the EDAC test is using locations that are free of errors.
SEP 84
3-2
Error message:
Single-bit error detected
Board: X
Syndrome Code:
~yyy
Chip Number: UZZZZ
Where: X" 0/1
YYY " Octal Syndrome Code
UZZZZ '" Reference
De~ignator
of faulty RAM