Data Processing Instruction Timings - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.8.3

Data Processing Instruction Timings

Table 4-5. Data Processing Instruction Timings
Instruction
ADC
ADD
AND
BIC
CMN
CMP
EOR
MOV
MVN
ORR
RSB
RSC
SBC
SUB
TEQ
TST
† If the next instruction uses the result of the data processing for a shift by immediate or as Rn in a QDADD or
QDSUB, one extra cycle of result latency is added to the number listed above
4-38
<shifter operand> Is Not a Shift/Rotate
by Register
Minimum Issue Minimum Result
Latency Latency
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Intel® PXA27x Processor Family Optimization Guide
<shifter operand> is a Shift/Rotate by
Register Or
<shifter operand> is RRX
Minimum Issue
†
Latency
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Minimum Result
†
Latency
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2