Thumb* Instructions; Instruction Latencies For Intel® Wireless Mmx™ Technology - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.8.11

Thumb* Instructions

In general, the timing of THUMB* instructions is the same as their equivalent ARM* instructions,
except for these cases:
•
If the equivalent ARM* instruction maps to an entry in
Latency with branch misprediction" goes from 5 to 6 cycles. This is due to the branch latency
penalty.
•
If the equivalent ARM* instruction maps to one in
when the Branch is Taken" increases by one cycle. This is due to the branch latency penalty.
•
The timings of a THUMB* BL instruction and an ARM* data processing instruction when
H=0 are the same.
The mapping of THUMB* instructions to ARM* instructions can be found in the
ARM*Architecture Reference Manual
4.9 Instruction Latencies for Intel® Wireless MMX™
Technology
The issue cycle and result latency of all the PXA27x processor instructions is shown in
In this table, the issue cycle is the number of cycles that an instruction takes to leave the register
file. The result latency is the number of cycles required to calculate the result and make it
available to the bypassing logic. A result latency of 1 indicates that the value is available
immediately to the following instruction.
degraded by data or resource hazards.
Table 4-18. Issue Cycle and Result Latency of the PXA27x processor Instructions (Sheet 1 of
2)
Intel® PXA27x Processor Family Optimization Guide
Instructions
WADD
WSUB
WCMPEQ
WCMPGT
WAND
WANDN
WOR
WXOR
WAVG2
WMAX
WMIN
WSAD
WACC
WMUL
WMADD
Table
Table 4-4, the "Minimum Issue Latency
Table 4-18 shows the best case result latency that can be
Issue Cycle Result Latency
1 1
1 1
1 2
1 2
1 1
1 1
1 1
1 1
1 1
1 2
1 2
1 1
1 1
1 1
1 1
4-3, the "Minimum Issue
Table 4-18.
4-43