Semaphore Instructions; Cp15 And Cp14 Coprocessor Instructions; Miscellaneous Instruction Timing - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.8.8

Semaphore Instructions

Table 4-13. Semaphore Instruction Timings
Instruction
SWP
SWPB
4.8.9

CP15 and CP14 Coprocessor Instructions

Table 4-14. CP15 Register Access Instruction Timings
Instruction
†
MRC
MCR
† MRC to R15 is unpredictable / MRC and MCR to CP0 and CP1 is described in the Intel® Wireless MMX™ Technology
section
Table 4-15. CP14 Register Access Instruction Timings
Instruction
MRC
MRC to R15
MCR
LDC
STC
4.8.10

Miscellaneous Instruction Timing

Table 4-16. Exception-Generating Instruction Timings
Instruction
SWI
BKPT
UNDEFINED
Table 4-17. Count Leading Zeros Instruction Timings
Instruction
CLZ
4-42
Minimum Issue Latency
5
5
Minimum Issue Latency
4
2
Minimum Issue Latency
8
9
8
11
8
Minimum latency to first instruction of exception handler
Minimum Issue Latency
1
Intel® PXA27x Processor Family Optimization Guide
Minimum Result Latency
5
5
Minimum Result Latency
4
N/A
Minimum Result Latency
8
9
N/A
N/A
N/A
6
6
6
Minimum Result Latency
1