Intel PXA270 Optimization Manual page 139

Index
A
1
About This Document
Alternate Memory Clock Setting 2
Arbiter Functionality 15
Arbitration Scheme Tuning for LCD 14
ARM* V5TE Instruction Execution 3
Array Merging 6
B
Bandwidth and Latency Requirements for LCD 11
Behavioral Description 6
Bit Field Manipulation 6
Branch Instruction Timings 37
Branch Instruction Timings (Those Not Predicted By the
37
BTB)
Branch Instruction Timings (Those Predicted By the BTB
(Branch Target Buffer))
Buffer for Capture Interface 9
Buffer for Context Switch 10
C
C and C++ Level Optimization 1
Cache Blocking 8
Cache Configuration 6
Noncacheable Regions 6
Read Allocate and Read-write Allocate Memory Regions
6
Write-through and Write-back Cached Memory Regions
6
5
Caches
Case Study 1
Memory-to-Memory Copy 29
Case Study 2
Optimizing Memory Fill 30
Case Study 3
Dot Product 31
Case Study 4
Graphics Object Rotation 32
Case Study 5
8x8 Block 1/2X Motion Compensation 33
Choosing Data Types 12
Code Optimization for Power Consumption 1
Code Placement to Reduce Cache Misses 5
Coding Technique
Pointer Preload 5
Preload to Reduce Register Pressure 6
Unrolling With Preload 4
Coding Technique with Preload 4
Conditional Instructions and Loop Control 1
Intel® PXA27x Processor Family Optimization Guide
37
Coprocessor Interface Pipeline 49
Count Leading Zeros Instruction Timings
CP14 Register Access Instruction Timings
CP15 and CP14 Coprocessor Instructions 42
CP15 Register Access Instruction Timings
Creating Scratch RAM in Data Cache 7
Creating Scratch RAM in the Internal SRAM 6
Cycle Distance from A to B 35
D
D1 and D2 Pipestage 5
D1 Stage 9
D2 Stage 9
Data Alignment For Maximizing Cache Usage 12
Data Alignment Techniques 25
Data Cache and Buffer Behavior when X = 0
Data Cache and Buffer Behavior when X = 1
Data Cache and Buffer operation comparison for Intel® SA-
1110 and Intel XScale® Microarchitecture, X=0
Data Hazards 45
Data Processing Instruction Timings 38
Data Processing Instruction Timings
Deep Idle Mode 2
Deep-Idle Mode 7
Deep-Sleep Mode 2, 7
Determining the Optimal Weights for Clients 15
6
DMA Controller
DWB Stage 9
Dynamic Adaptation of Weights 16
E
Effective Use of Addressing Modes 8
Efficient Usage of Preloading 1
Exception-Generating Instruction Timings
Execute (X1) Pipestages 4
Execute 2 (X2) Pipestage 5
Execute Pipeline Thread 7
Execution Pipeline 46
External Memory Bus Buffer Strength Registers 5
External Memory Controller
External SDRAM Access Latency and Throughput for Differ-
ent Frequencies (Silicon Measurement Pending)
F
F1 / F2 (Instruction Fetch) Pipestages 3
Fast-Bus Mode 4
Frame Buffer Placement for LCD Optimization 13
42
42
42
3
3
38
42
5
Index-1
4
1