Intel PXA270 Optimization Manual page 4

Contents
2.3.2.1
2.3.2.2
2.3.2.3
2.3.2.4
2.3.3 Memory Pipeline Thread.......................................................................................2-9
2.3.3.1
2.3.3.2
2.3.3.3
3 System Level Optimization........................................................................................................3-1
3.1 Optimizing Frequency Selection ........................................................................................3-1
3.2 Memory System Optimization............................................................................................3-1
3.2.1 Optimal Setting for Memory Latency and Bandwidth............................................3-1
3.2.2 Alternate Memory Clock Setting ...........................................................................3-2
3.2.3 Page Table Configuration .....................................................................................3-3
3.2.3.1
3.2.3.2
3.3 Optimizing for Instruction and Data Caches ......................................................................3-4
3.3.1 Increasing Instruction Cache Performance...........................................................3-4
3.3.1.1
3.3.1.2
3.3.1.3
3.3.2 Increasing Data Cache Performance....................................................................3-5
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
3.3.2.5
3.3.2.6
3.3.3 Optimizing TLB (Translation Lookaside Buffer) Usage.........................................3-8
3.4 Optimizing for Internal Memory Usage ..............................................................................3-9
3.4.1 LCD Frame Buffer.................................................................................................3-9
3.4.2 Buffer for Capture Interface ..................................................................................3-9
3.4.3 Buffer for Context Switch ....................................................................................3-10
3.4.4 Scratch Ram .......................................................................................................3-10
3.4.5 OS Acceleration..................................................................................................3-10
3.4.6 Increasing Preloads for Memory Performance ...................................................3-10
3.5 Optimization of System Components ..............................................................................3-10
3.5.1 LCD Controller Optimization ...............................................................................3-11
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.4
3.5.1.5
3.5.2 Optimizing Arbiter Settings .................................................................................3-15
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
3.5.3 Usage of DMA ....................................................................................................3-17
3.5.4 Peripheral Bus Split Transactions.......................................................................3-17
iv
M1 Stage...............................................................................................2-8
M2 Stage...............................................................................................2-8
M3 Stage...............................................................................................2-8
MWB Stage...........................................................................................2-8
D1 Stage ...............................................................................................2-9
D2 Stage ...............................................................................................2-9
DWB Stage ...........................................................................................2-9
Page Attributes For Instructions............................................................3-3
Page Attributes For Data Access..........................................................3-3
Round Robin Replacement Cache Policy.............................................3-5
Code Placement to Reduce Cache Misses ..........................................3-5
Locking Code into the Instruction Cache ..............................................3-5
Cache Configuration .............................................................................3-6
Creating Scratch RAM in the Internal SRAM ........................................3-6
Creating Scratch RAM in Data Cache ..................................................3-7
Reducing Memory Page Thrashing ......................................................3-7
Using Mini-Data Cache .........................................................................3-8
Reducing Cache Conflicts, Pollution and Pressure ..............................3-8
Bandwidth and Latency Requirements for LCD..................................3-11
Frame Buffer Placement for LCD Optimization...................................3-13
LCD Display Frame Buffer Setting......................................................3-14
LCD Color Conversion HW .................................................................3-14
Arbitration Scheme Tuning for LCD ....................................................3-14
Arbiter Functionality ............................................................................3-15
Determining the Optimal Weights for Clients ......................................3-15
Taking Advantage of Bus Parking.......................................................3-16
Dynamic Adaptation of Weights..........................................................3-16
Intel® PXA27x Processor Family Optimization Guide