Table Of Contents - Intel PXA270 Optimization Manual

Contents
1 Introduction.................................................................................................................................1-1
1.1 About This Document ........................................................................................................1-1
1.2 High-Level Overview..........................................................................................................1-2
1.2.1 Intel XScale® Microarchitecture and Intel XScale® core......................................1-3
1.2.2 Intel XScale® Microarchitecture Features ............................................................1-4
1.2.3 Intel® Wireless MMX™ technology ......................................................................1-4
1.2.4 Memory Architecture.............................................................................................1-5
1.2.4.1
1.2.4.2
1.2.4.3
1.2.5 Processor Internal Communications .....................................................................1-5
1.2.5.1
1.2.5.2
1.2.5.3
1.2.6 Wireless Intel Speedstep® technology .................................................................1-7
1.3 Intel XScale® Microarchitecture Compatibility...................................................................1-8
1.3.1 PXA27x Processor Performance Features ...........................................................1-8
2 Microarchitecture Overview ......................................................................................................2-1
2.1 Introduction ........................................................................................................................2-1
2.2 Intel XScale® Microarchitecture Pipeline...........................................................................2-1
2.2.1 General Pipeline Characteristics...........................................................................2-1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2 Instruction Flow Through the Pipeline ..................................................................2-2
2.2.2.1
2.2.2.2
2.2.3 Main Execution Pipeline .......................................................................................2-3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
2.2.3.6
2.2.4 Memory Pipeline ...................................................................................................2-5
2.2.4.1
2.2.5 Multiply/Multiply Accumulate (MAC) Pipeline........................................................2-5
2.2.5.1
2.2.5.2
2.3 Intel® Wireless MMX™ Technology Pipeline ....................................................................2-7
2.3.1 Execute Pipeline Thread.......................................................................................2-7
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.1.5
2.3.2 Multiply Pipeline Thread .......................................................................................2-8
Intel® PXA27x Processor Family Optimization Guide
Caches ..................................................................................................1-5
Internal Memories .................................................................................1-5
External Memory Controller ..................................................................1-5
System Bus ...........................................................................................1-5
Peripheral Bus ......................................................................................1-6
Peripherals in the Processor .................................................................1-6
Pipeline Organization............................................................................2-1
Out of Order Completion .......................................................................2-2
Use of Bypassing ..................................................................................2-2
ARM* V5TE Instruction Execution ........................................................2-3
Pipeline Stalls .......................................................................................2-3
F1 / F2 (Instruction Fetch) Pipestages ..................................................2-3
Instruction Decode (ID) Pipestage ........................................................2-4
Register File / Shifter (RF) Pipestage ...................................................2-4
Execute (X1) Pipestages ......................................................................2-4
Execute 2 (X2) Pipestage .....................................................................2-5
Write-Back (WB) ...................................................................................2-5
D1 and D2 Pipestage............................................................................2-5
Behavioral Description ..........................................................................2-6
Perils of Superpipelining .......................................................................2-6
ID Stage ................................................................................................2-7
RF Stage ...............................................................................................2-7
X1 Stage ...............................................................................................2-8
X2 Stage ...............................................................................................2-8
XWB Stage ...........................................................................................2-8
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