Intel PXA270 Optimization Manual page 92

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
Table 4-18. Issue Cycle and Result Latency of the PXA27x processor Instructions (Sheet 2 of
2)
WLDR (BHW) to main regfile
WLDRW to control regfile
†
WLDRD is 4 cycles WLDR<B,H,W> is 3 cycles
††
Base address register update for
load/store operation
4-44
Instructions
WMAC
TMIA
TMIAPH
TMIAxy
WSLL
WSRA
WSRL
WROR
WPACK
WUNPCKEH
WUNPCKEL
WUNPCKIH
WUNPCKIL
WALIGNI
WALIGNR
WSHUF
TANDC
TORC
TEXTRC
TEXTRM
TMCR
TMCRR
TMRC
TMRRC
TMOVMSK
TINSTR
TBCST
WSTR
WLDR
and
Issue Cycle Result Latency
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 4 (3)
1 4
1 na
WSTR is the same as the core
Intel® PXA27x Processor Family Optimization Guide
2
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
2
3
1
2
3
2
1
1
† ††
,
††
††