Instruction Latencies For Intel Xscale® Microarchitecture; Performance Terms - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
The IPP include optimized general signal and image processing primitives, as well as primitives for
use in constructing internationally standardized audio, video, image, and speech encoder/decoders
(CODECs) for the PXA27x processor.
IPP available for general one-dimensional (1D) signal processing include:
•
Vector initialization, arithmetic, statistics, thresholding, and measure
•
Deterministic and random signal generation
•
Convolution, filtering, windowing, and transforms
IPP for general two-dimensional (2D) image processing include:
•
Vector initialization, arithmetic, statistics, thresholding, and measure
•
Color conversions
•
Morphological operations
•
Convolution, filtering, windowing, and transforms
Additional IPP are available allowing construction of these multimedia CODECs:
•
Video - ITU H.263 decoder, ISO/IEC 14496-2 MPEG-4 decoder
•
Audio - ISO/IEC 11172-3 and 13818-3 (MPEG-1, -2) Layer 3 ("MP3") decoder.
•
Speech - ITU-T G.723.1 CODEC and ETSI GSM-AMR codec
•
Image - ISO/IEC JPEG CODEC
For more details on the IPP, as well as upcoming libraries for 3D graphics and encryption, browse
http://intel.com/software/products/ipp/.
4.8 Instruction Latencies for Intel XScale®
Microarchitecture
The following sections show the latencies for all the instructions with respect to their functional
groups: branch, data processing, multiply, status register access, load/store, semaphore, and
coprocessor.
Section 4.8.1, "Performance Terms"
4.8.1

Performance Terms

•
Issue Clock (cycle 0)
The first cycle when an instruction is decoded and allowed to proceed to further stages in the
execution pipeline.
•
Cycle Distance from A to B
The cycle distance from cycle A to cycle B is (B-A) — the number of cycles from the start of
cycle A to the start of cycle B. For example, the cycle distance from cycle 3 to cycle 4 is one
cycle.
Intel® PXA27x Processor Family Optimization Guide
explains how to read Table 4-2 through Table 4-17.
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