Unsigned Unpack Example - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
Table 4-1. PXA27x processor Mapping to Intel® Wireless MMX™ Technology and SSE (Sheet
2 of 2)
PXA27x processor
WPACK{h/w}{US}
WAND
WANDN
WOR
WXOR
WMOV/WLDR
WMAX{B}{U}
WMAX{H}{S}
WMIN{B}{U}
WMAX{H}{S}
TMOVMSK{B}
WAVG2{B,W}
TINSR{W}
TEXTRM{W}
WSAD{B,W}
WSHUFH
Following is a set of examples showing subtle differences between Intel® MMX™ Technology
and Intel® Wireless MMX™ Technology codes. The number of cases have been limited for the
sake of brevity.
4.5.2

Unsigned Unpack Example

The Intel® Wireless MMX™ Technology provides instructions for unpacking 8 bit, 16 bit, or
32 bit data and either sign-extending or zero extending.
The unsigned unpack replaces the Intel® MMX™ Technology sequence:
Intel® Wireless MMX™ Technology
Instructions
Instructions
Input: wR0
WUNPCKELU
WUNPCKEHU
4-28
Intel® Wireless
MMX™ Technology
PACKUS{wb/dw}
PAND
PANDN
POR
PXOR
MOV{d/q}
—
—
—
—
—
—
—
—
—
—
: Source Value
wR1 , wR0
wR2 , wR0
Intel® PXA27x Processor Family Optimization Guide
SSE Comments
—
—
—
—
—
—
PXA27x processor is a
PMAXUB
superset
PXA27x processor is a
PMAXSW
superset
PXA27x processor is a
PMINUB
superset
PXA27x processor is a
PMIXSW
superset
PMOVMSKB Transfer instruction
PXA27x processor is a
PAVG{BW}
superset
PXA27x processor is a
PINSRW
superset
PXA27x processor is a
PEXTRW
superset
PSAD{BW}
PSHUFW
Intel® MMX™ Technology
Input: mm0
mm7
MOVQ
PUNPCKLWD
PUNPCKHWD
: Source Value
: 0
mm1, mm0
mm0, mm7
mm1, mm