Multiply Pipeline - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
Table 4-19. Resource Availability Delay for the Execution Pipeline (Sheet 2 of 2)
† The WSAD, TMIA, TMIAph, TMIAxy execute in both the
main execution pipeline and the multiplier pipeline. They
execute for one cycle in the execution pipeline and the
rest in the multiplier pipeline. See
more details
4.10.2.2

Multiply Pipeline

Instructions issued to the multiply pipeline may take up to two cycles before another instruction
can be issued to the pipeline. The instructions in the multiply pipe can be categorized into 4 classes
shown in
multiplier pipeline depend upon the class of the multiply instruction that subsequently wants to use
the multiply resource. These delays for are shown below in
instruction is followed by a TMIAph (class3) instruction, then the TMIAph sees a resource
availability of 2 cycles.
Intel® PXA27x Processor Family Optimization Guide
Instructions
WAVG2
WMAX
WMIN
WSAD
WSLL
WSRA
WSRL
WROR
WPACK
WUNPCKEH
WUNPCKEL
WUNPCKIH
WUNPCKIL
WALIGNI
WALIGNR
WSHUF
TMIA
TMIAph
TMIAxy
TMCR
TMCRR
TINSR
TBCST
TANDC
TORC
TEXTRC
Section 4.10.2.5
Table 4-20. The resource-availability delay for the instructions that are mapped onto the
Delay (Clocks)
1
1
1
†
1
1
1
1
1
1
1
1
1
1
1
1
1
1 †
†
1
†
1
1
1
1
1
1
1
1
for
Table 4-21. For example if a TMIA
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