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The Intel XScale® Microarchitecture allows individual entries to be locked in the TLBs. Each
locked TLB entry reduces the number of TLB entries available to hold other translation
information. The entries one would expect to lock in the TLBs are those used during access to
locked cache lines. A TLB global invalidate does not affect locked entries.
The TLBs can be used translate a virtual address to the physical address. The hardware page-table
walk eliminates the page translation task for the OS. From the performance point of view, HW
TLBs are more efficient than SW managed TLBs. It is recommended that HW TLBs are used for
page table walking - however, to reduce data aborts the page table attributes need to be set
correctly. During context switch, OS implementation may choose to flush the TLBs. However, the
OS is free to lock critical TLB entries in the TLBs reduce excessive thrashing and hence retain
performance.
3.4
Optimizing for Internal Memory Usage
The PXA27x processor has a 256 Kbyte memory which offers low latency and high memory
bandwidth. Any data structure which requires high throughput and lower latency can be placed in
the internal memory. While the LCD frame buffer is highly likely to be mapped to the internal
memory, depending on the LCD size and refresh rate and latency that LCD can tolerate, some
overlays can be placed in the external memory. This scheme may free up some internal memory
space for OS and user applications. Depending on the user profile the internal memory can be used
for different purposes.
3.4.1
LCD Frame Buffer
The LCD is a significant bandwidth consumer in the system. The LCD frame buffer can be mapped
to the internal memory. Apart from using the LCD frame buffer, the internal memory space may be
used for an application frame buffer. Many applications update the image to be displayed in their
local copy of frame buffer and then copy the content into the LCD frame buffer. Depending on the
application's update rate and LCD size, it might be preferable to allow the application to update the
application's frame-buffer, while system DMA can copy from the application's frame-buffer to the
LCD frame-buffer.
The LCD controller uses its DMA controller to fetch data from the frame buffer. This makes it
possible to split the frame buffers between internal SRAM and external memory, if necessary,
through the use of chained DMA descriptors. In this way it is possible to uses the internal SRAM
for a portion of the frame buffer, even if the entire frame buffer cannot fit within the 256KB.
3.4.2
Buffer for Capture Interface
The capture frames at the camera interface are typically processed for image enhancements and
often encoded for transmission or storage. The image enhancement and video encoding application
is accelerated by allowing the storage of the raw data in the internal memory. Note that the capture
interface can be on-board or be an external device. Both benefit from the use of the internal
memory buffering scheme.
Intel® PXA27x Processor Family Optimization Guide
System Level Optimization
3-9
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