•
PID register for fast virtual address remapping
•
Vector remap
•
Interrupt controller offers faster interrupt latency with the help of programmable priority
sorting mechanism.
•
Extensions to the exception model to include imprecise data and instruction preload aborts
•
Access control to other coprocessors
•
Enhanced set of supported cache-control options
•
A branch target buffer for dynamic-branch prediction
•
Performance monitoring unit
•
Software-debug support, including instruction and data breakpoints, a serial debug link via the
JTAG interface and a 256-entry trace buffer
•
Integrated memory controller with support for SDRAM, flash memory, synchronous ROM,
SRAM, variable latency I/O (VLIO) memory, PC card, and compact flash expansion memory.
•
Six power-management modes
Intel® PXA27x Processor Family Optimization Guide
Introduction
1-9