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Introduction
•
Six power modes to control power consumption:
— Normal
— Idle
— Deep idle
— Standby
— Sleep
— Deep sleep
•
Programmable I
See the Intel® PXA27x Processor Family Developer's Manual for more details.
1.3
Intel XScale® Microarchitecture Compatibility
The Intel XScale® Microarchitecture is ARM*Version 5 (V5TE) architecture compliant. The
PXA27x processor implements the integer instruction set architecture of ARM*V5TE.
Backward compatibility for user-mode applications is maintained with the earlier generations of
StrongARM* and Intel XScale® Microarchitecture processors. Operating systems may require
modifications to match the specific Intel XScale® Microarchitecture hardware features, and to take
advantage of the performance enhancements added to this core.
Memory map and register locations are backward-compatible with the previous Intel XScale®
Microarchitecture hand-held products.
The Intel® Wireless MMX™ technology instruction set is compatible with the standard ARM*
coprocessor instruction format (See The Complete Guide to Intel® Wireless MMX™ Technology
for more details).
1.3.1
PXA27x Processor Performance Features
Performance features of the PXA27x processor are:
•
32-Kbyte instruction cache
•
32-Kbyte data cache
•
Intel® Wireless MMX™ technology with sixteen 64-bit registers, optimized instructions for
video, and multi-media applications.
•
The PXA27x processor has an internal SRAM of 256 KBytes.
•
Capability of locking entries in the instruction or data caches
•
2-Kbyte mini-data cache, separate from the data cache
•
L1 caches and the mini-data cache use virtual address indices (or tags)
•
Separate instruction and data Translation Lookaside buffers (TLBs), each with 32 entries
•
Capability of locking entries in the TLBs
•
16-channel DMA engine with transfer-size control and descriptor chaining
1-8
2
C-based external regulator interface to support voltage changing.
Intel® PXA27x Processor Family Optimization Guide
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