I/O Processing And Response Delay - Mitsubishi Electric MELSEC FX3U Programming Manual

Melsec fx series programmable logic controllers
Table of Contents

Advertisement

FX
/FX
/FX
Series Programmable Controllers
3G
3U
3UC
Programming Manual - Basic & Applied Instruction Edition
6.3

I/O Processing and Response Delay

1. Operation timing of I/O relays and response delay
FX PLCs execute the I/O processing by repeating
the process (1) to process (3).
Accordingly, the control executed by PLCs contains
not only the drive time of input filters and output
devices but also the response delay caused by the
operation cycle.
Acquiring the latest I/O information
For acquiring the latest input information or
immediately outputting the operation result in the
middle of the operation cycle shown above, the I/O
refresh instruction is available.
2. Short pulses cannot be received.
The ON duration and OFF duration of inputs in PLCs require longer time than "PLC cycle time + Input filter
response delay".
When the response delay of the input filter "10 ms" is considered and the cycle time is supposed as "10 ms",
the ON duration and OFF duration should be at least 20 ms respectively.
Accordingly, PLCs cannot handle input pulses at 25 Hz (1000 / (20 + 20) = 25) or more. However, the
situation can be improved by PLC special functions and applied instructions.
Convenient functions for improvement
By using the following functions, PLCs
can receive pulses shorter than the
operation cycle:
• High speed counter function
• Input interrupt function
• Pulse catch function
• Input filter value adjustment function
6 What to Understand before Programming
(1)
[Input
processing]
Input image
memory is read
(2)
Scan time
(operation
cycle)
Batch I/O method
(refresh method)
This "input ON" can be received
"Input ON" cannot
be received
OFF
ON
Program
Program
processing
processing
Input processing
Output processing
(
6.3 I/O Processing and Response Delay
The ON/OFF status of input
terminals is received at one time.
Input image is read,
and operation is
executed according
[Program processing]
to program.
Image memory of
each device is
updated
(3)
[Output processing]
Output
Result is
devices
transferred to
output latch
are driven
memory
This "input OFF"
cannot be received
OFF
ON
Program
Program
processing
processing
Operation cycle
Time)
1
2
3
4
5
6
7
8
9
10
177

Advertisement

Table of Contents
loading

This manual is also suitable for:

Melsec fx3ucMelsec fx3g

Table of Contents