Epson PX-8 Technical Manual page 65

REV.-A
When the Z-INT signal is activated, the main CPU samples the signal at the rising edge of the
clock signal in the last state of the current instruction execution and generates an M 1 cycle which
includes two extra wait cycles. Then, the CPU reads data (a vector address) from GAH40M at the
rising edge of T3 in the M 1 cycle and begins the interrupt processing.
Observed Memory Control Signal Waveforms
(Top) ClK:
Measured at 4A, pin 6
(Second from top) M 1 :
Measured at 4A, pin 27
(Second from bottom) MRQ
Measured at 4A, pin 19
(Bottom) RF:
Measured at 4A, pin 28
(Top)
ClK:
Measured at 4A, pin 6
(Second from top) MRQ:
Measured at 4A, pin 19
(Second from bottom) RF:
Measured at 4A, pin 28
(Bottom) RD:
Measured at 4A, pin 21
2-41
G
G
G
G
5V 5V >500nS
nno.no
f1JUQl1JU
n.
QJ
1.
.8
an.
It].
,b.
,t
5V 5V
Fig. 2-36 ClK, M1, MRQ, and RF
5V
5V >200nS
GQoOOOOO[
G
n
n~
n.D.
G \
A1"
~q
L
GJ_~_'
__
A_·~l
__
w~r~·
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__
5V 5V
Fig. 2-37 ClK, MRQ, RF, and RD