Gate Array Gah40M - Epson PX-8 Technical Manual

REV.-A
7.5 Gate Array GAH40M (E01031AA)
This gate array incorporates the following functional blocks; the operation is controlled by the
Z80 main CPU.
Address bus
RD, WR, 10RQ
M1
Data bus
82C51 1320
RS-232C 7508
7508 7508 7508
CS CS
LED SI
SO RDY ISIO
I
/~
Ir. I
A
I(
Address
....
-
lOR
I(
decoder
~
Serial I/O
t--
register
....
lOW
I
1
<II
>-
Control
,
register
l' - }
Intemal
RDY SIO
~
register
A
-,. select line
~
7
,Ii
..
....
j
<II
>-
~U
<II
>-
<II
I
L
-v
~~~ I
Ql
OJ
"0
...
~
r?
c.:;:
2 0
.... C
Ql..¥,
...
(.)
Era
04W
[8
I
Interrupt
vectoring
4
jlI.
Interrupt
priority
<IIr
Interrupt
signal
I
...
Input capture
0.
register
::J~
.... Vl
~
.... ::J
Ql'"
4
jlI.
<II
... ra
c ...
:=.Vl
~
>-
04R
r1
Free running
counter
Clock
INTO (7508) 614.4 KHz
INT1 (82C51)
INT2 (RS-232C: DCD)
INT2 (6303)
INT5 (EXT)
Fig. 7-5
Control
register
....
f--?
....
0
r
"V
...
(.)
Ql
Qi
en
~
RXC
TXC
As shown in Fig. 7-5, this gate array includes the address decoder, the 7508 interface, an inter-
rupt controller, a timer and baud rate generator, and I/O ports for the RS-232C and the LED dis-
play.
7-17