Epson PX-8 Technical Manual page 174

REV.-A
3.2.8 Bank Control
The RAM disk unit can contain a 4 K byte IPL ROM and 64 K or 128 K byte DRAM. However, the
Z-80 CPU cannot directly access DRAM above 64 K bytes. Thus, DRAM needs to be divided into
banks so that entire DRAM can be accessed indirectly by selecting bank. This control is accom-
plised by the Bank Latch circuit and the gate array GAH40D shown in fig. 3-38.
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AO
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02 (W) _+-i'
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1
I
R
1 . Momory map
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68
6
1 ,
I I
DO
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07
Fig. 3-38 Bank Control Circuit
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EOI030EA
(GAH40D)
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The bank control signals and the memory map are associated as shown in table 3-9.
Table 3-9 Bank Control Signal and Memory Map
i:~
1
1 0
0
BK
Address 0/1
0
1
0
1
FFFF
(FeOO)
.... . .......
DRAM 2
DRAM 2 DRAM 1
DRAM 1
(OFFF)
IPL ROM
IPL ROM
0000
Note:
The DRAM address space from FCOO to FFFF is a comon area which contains the bank se-
lection program.
3-28