Dram ,Upd4265 - Epson PX-8 Technical Manual

REV.-A
7.12 DRAM ,uPD4265
This DRAM is a 64K x 1 bit quasi-CMOS chip, which reduces power consumption. It is used
only at the output section. It can be refreshed in two modes: an automatic, self refresh, which
-
- -
uses the RF signal at pin 1; and a hidden refresh, which uses the CAS signal at pin 15. While
power is off, the sub-CPU 7508 provides three modes for saving reducing power consumption.
Those modes are automatically selected depending on sensed ambient temperature.
Figs. 7-22 and 7-23 respectively show the Timing relationships among major control signals in
the read and write cycles.
(Read cycle)
RAS
\ / \
CAS
\ / \...
Address
=x
ROW
'0
COLUMN
X
X
ROW
x=
WE
DO
<
Valid read data
)
Fig. 7-22 DRAM Read Cycle Operation Timing
(Write cycle)
RAS------~,,~
________________________ __ / \
CAS
------------------~,,~
______________
~
/ \...
X
Address
=x
ROW
'O __
C_O_L_U_M_N_--IX .... _ _ _ _ _ _ _
...J
ROW
x=
WE
------------~
DI
______________ .Jx
Valid read data
X . . . . ___________________ _
-------------------------------OPEN----------------------------
Fig. 7-23 DRAM Write Cycle Operation Timing
7-57