Gate Array Gah40S - Epson PX-8 Technical Manual

REV.-A
7.6 Gate Array GAH40S
Gate array GAH40S, which is controlled by the 6303 slave CPU, in turn controls the microcas-
sette tape drive, LCD controller, and ROM capsule. It consists of three segments: an address de-
coder, a microcassette tape drive interface, and a P-ROM interface. Figs. 7-12 through 7-14 are
functional block diagrams of these blocks.
(1) Address decoder block
AB15,14
ASRW, E
ADB7
~O
IROO
r
r
L
(2) P-ROM interface block
+5V
GAH40S
Data bus
c:
a..
~
CJ)
-'
Address
decoder
IlPROM
J
address register
lPROM rl
data buffer
'(
Interrupt
r1
I
Counter
11
lcommand
mask resister
J
Counter
input sampler
I
CNTR MT
Fig. 7-12 Address decoder block diagram
PROM#l
PROM#2
PROM
nterface i
MCT
interface
-------------------------------------------------------
Fig. 7-13 P-ROM Interface Block Diagram
7-29