Epson PX-8 Technical Manual page 178

3.2.12 Jumpers and Switch
The combination of jumper J 1 and switch SW1
allows the IPL program to be read via I/O port
address 01. Jumper J2 selects a CPU model.
D 1
======::;::t=========
DO--------~~------------
D1R----~
3.2.13 Status Register
LOGIC
Vee
Fig. 3-44
REV.-A
Backup line
E80 GAH40P
The Main Frame CPU reads the RAM disk status from IC "1 OC" shown in fig. 3-45. Input termin-
als 6 and 10 are grounded to produce the ID code of the RAM disk unit. The Date/COM Write sig-
nal input to terminal 4 indicates whether a data or command received from Main Frame is being
processed or not. The signal input to terminal 2 from D-type FF "12C" indicates whether a data is
latched (buffered) to be sent to Main Frame or not.
ta set da
(00 W)-option
tus read
sta
(81 R) .... Main frame
DA TA/CMD
a read dat
(80
K)
sta
81
tus read
P
I
GATE
3(1
9~
s?
nU:H~4K R~
1·
Q 112C)
5
2 4 i 6 P
I H
6
~k ;I~
GI
115
35
79
I.
,\
Fig. 3-45 DRAM Circuit Organization
3-32
RM3
,J
~.2
34 5678 8
11'01,10
9
a
E
81~ I
119
7 H B'[
A6
2
1!6~"'
AS 4 BS T1 ,\:"
4
5
9
4 ,1 (,
3
S1~
I
2 B2
I(SA) 81
OIR 3.JK
.a
I[
17 II
0
I 2
j~
?Cf?