Epson PX-8 Technical Manual page 170

While Main Frame Power is on, no effective po-
tential is generated across the emitter and base
of Q1 because the base is pulled up to VL, and
Q 1 is maintained cut off. Q4 conducts because
the base input (VL) is low and the collector is
held low. This maintains Q2 and Q3 in conduc-
tion. Thus, the backup line is powered via Q2
and the logic circuit voltage is supplied through
Q3.
3. Logic circuit voltage
The logic circuit voltage is supplied from the
collector of transistor Q3. The voltage ap-
plied to the emitter (V81 or V
CH
through D1
and R34) is supplied to the circuit power
line. The supply circuit operates as descried
above.
3.2.6 Interface Circuit
39
v
C
H
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V
B
,
R37 33 K
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R38
B808e;
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D9
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Fig. 3-33 Power Supply Circuit
REV.-A
Since this RAM disk unit and Main Frame asynchronously operate, either one must examine the
status of the other to accomplish a RAM disk read/write. A function, which temporarily stores the
data until it is written in RAM disk or read by Main Frame, is also required.
1. Address decoder
The RAM disk is looked upon as an I/O de-
vice by the Main Frame CPU and two I/O ad-
dresses are assigned. Fig. 3-34 shows the
address decoder circuit.
...-
I
o
R
Q
210
RMi
1M x
8
7
81H
Pin 10 and 13 of IC "6C" are the outputs of
the decoder. As obvious from the figure, the
output (pin 8) of IC "68" must be low to ena-
ble the two decoder outputs. Either of them
is selected depending on the state of AO.
The output IC "68" is low when the following
relation is satisfied among the input signals
to this IC and the preceding IC "7C"; A 1 - A6
.A7.IORQ. This relation can be logically re-
presented as in Fig. 3-34; an address 80 (H)
or 81
(H)
is decoded to access the RAM disk
unit.
Fig. 3-34
A3 A2
RAM disk address decoder circuit
A7 A6 A5 A4 A1 AO
o o
o
o
o
~~----------------~--------------~)
L - -_ _ _ _ _ _ _ _ _ _ _
j:~
(H)
81 (H)
3-24