Epson PX-8 Technical Manual page 151

REV.-A
Table 3-1 Cassette Tape Operation Truth Table
I---o-,-p_e_ra_t_io __ n _ _ _
~~c
,
MTB i MT A
~::~J
Head Position
READ (Replay) I
0 i 0
~
: 0
---11~~L_o_ad
__
~
_ _ _ _ _ _ _ _ _
---I
WRITE (REG)
0
I
0
I
1
I
1 -l-_L_o_a_d _ _ _ _ _ _ _ . ______
--l
REWIND (FAST) 1 I 1
0
I
0
i
Unload
REWIND (SLOW)
··1-
~
I 1 O!
0
1-
. --U-nl-o-·-ad------~~~~--~---l
I---F-.-F.-(-F-A-S-T-)
------+1
1 I
0
~T~-- I --U·-n-Io-a--d--------------------
1 - - - - - - - - - - - - - - -
--+--~_+_-+--------+--------------------
F.F. (SLOW)
I
0
I
0
!
1
I
0 i Unload
MTA
=
High, MTB
=
Low
Since both the signals are supplied to the exclusive OR gate
A.
the base of the transistors 02 and
03 are held high, maintaining them in conduction. This causes the emitter of 02 to be held high
which in turn maintains transistor 07 in conduction, holding the M- terminal of the capstan motor
at ground level. The low signal inverted by inverter C turns transistor 04 on which drives the ex-
ternal transistor 01, supplying the VBSW voltage to the M+ terminal of the capstan motor. This
results in a forward capstan motor drive which winds the tape. (The motor control transistors 04
and A7 are in conduction.)
MTA
=
Low, MTB
=
High
Both 02 and 03 are in conduction similare to the above phase. However, the high level at the col-
lector of 03 maintains the transistor in conduction this time, causing the the M+ terminal of the
capstan motor to be held at ground level. The low signal inverted by inverter D turns transistor
06 and supplies the VBSW voltage to the M- terminal. This results in a backward capstan motor
drive, which rewinds the tape. (The motor control transistors, 05 and 06, are in conduction.)
MTA = High, MTB = High
When both the signals are high, the low output of the exclusive OR gate A cuts off transistors 02
and 03, and no effective control signal can be output at the emitter of either transistor, but the
high level output of AND gate B maintains transistors 05 and 07 in conduction, holding both the
M+ and M- terminals of the capstan motor at ground level. (The motor control transistors 05 and
07 are in conduction.)
MTA = Low, MTB = Low
Both the outputs of the exclusive OR gate A and the AND gate B are low; no control signal is avai-
lable. All the motor control transistors, 04 through 07, are cut off, leaving the capstan motor in a
floating state.
The external transistor 01 is controlled by the output at pin 6 of IC2 (a speed control signal).
Thus, the VBSW voltage may not be supplied to the capstan motor if either 04 or 06 is in conduc-
tion.
3-5