Epson PX-8 Technical Manual page 175

REV.-A
Gate GAH40D is initialized as follows when Main Frame Power is turned on:
Bank 2 = 1, Bank 0/1 = 0
This initialization is of course accomplished by a hardware reset logic. The initialization circuit
operation is described below .
• The Reset (R) signal is connected to both the Bank Latch FFs located in drawing coordinations
C,D-3. Thus, the two Q outputs are held-low - the output from pin 5 is the Bank 0/1 Selection
signal and the output from pin 9 is the Bank 2 Selection signal. Address bus lines 12 through
15 from the Z-80 CPU are respectively connected to pins 4, 2, 1, and 5 of IC "6B" which are all
low immediately after Main Frame power is turned on, raising the output (pin 6) high. This out-
put signal is fed to IC "13C" where it is NANDED with the Bank 2 Selection signal from the
Bank Latch circuit which is also low immediately after power on. Thus, the output from pin 3 is
high.
The RAM disk memory address space is mapped as shwon in the second (from the left) or fourth
column of table 3-9 by initialization so that the CPU accesses address 0000; i.e., the IPL ROM
area.
2. Bank selection
Bank selection is accomplished by the program in IPL ROM which accesses I/O ADDRESS 02
and 03, which are connected to the Bank Latch, to change the latch setting. Thus, if a bank,
which allows no IPL ROM access, were selected by simply accessing the Bank Latch, no subse-
quent bank selection would be possible. In order to solve this problem, the bank control pro-
gram is usually written in the DRAM area from a certain address during the IPL program execu-
tion. This unit initially loads the bank control program in a DRAM 2 address space from FCOO
to FFFF, and a common DRAM 2 area of the highest 64 bytes is always selected independently
by gate array GAH40D regardless of bank (0/1 or 2).
3.2.9 Interrupt
As previously stated, the command (i.e., Read or Write) and 8-bit data sent from the Main Frame is
temporarily stored in an internal buffer because the RAM disk unit operates asynchronously. The
unit is notified of this temporary storage by an interrupt. Fig. 3-39 shows the interrupt circuit.
(1A)
,
M1
-
10RQ
-
INTR
r
(00-07)
3
6C
49
1
::J .r-.
~10
2
11
19 ')
- -
1
Z-INT 1G 2G
4
A2(11Cl 1Y2 16
1A3
W3 114
17
(1C)
A4
2<4
2: 1A 1 o:t
lY1 18
9
1A4
~
1Y4112
- -
til S-INT
8
7C
112A1
J: 2Y1 9
~
11 13
2Y2 7
2
15 2A3 i2Y3 5
7'7
DATA READ{SOR)
COMMAND WRITE(81W
Fig. 3-39 RAM Disk Interrupt Circuit
3-29
DATE WRITE.{SO
W )
00",07