Epson PX-8 Technical Manual page 101

REV.-A
In the above circuit, the Latch Pulse (LP) signal is supplied to the Enable Input (EI) terminal of the
first (i.e., X1) SED1120 driver. Once the X1 driver is enabled (the internal flipflop is set ON) with a
single LP signal pulse, the subsequent drivers X2 through X8 can be sequentially selected (or ena-
bled) by the XECL signal.
2.8.3.2 Data Transfer
Four data lines are connected to each SED1120 driver and four-bit data is serially transferred one
bit at a time. The data are transferred to a driver and are converted to parallel by an internal shift
register. Fig. 2-79 outlines the timing relationship among the LCD operation signals.
LP
XECL~----------~ ~
________
~ ~~/-
____
~n~
______________ __
XSCL
mruuut1UUlfAlULJUUlYtuuuuuV)JUUULJUlJ11
~
16 pulses
SED1120 X1 X2 X7
X8
X1
Chip select
XSCL
DINO
60
~
________________
~ ~
__________
~/~/
____
~fl~
____________ _
56 0
DIN1
~
________________
~ ~
______
~/~/
________
~rl~
________ __
57
61
DIN2
62
~
____________
~ ~
__
-7)~
______
~n~
__ __
58 2
DIN3
63
~-7}
_ _ _ _ _ _ _ _
~n~
__ _
59 3
Fig. 2-79 LCD Operation Signal Timing
16 pulses of the data strobing signal XSCL are supplied to each SED1120 driver. During each of
these pulses, data bits DINO through DIN3 are strobed. These data bits correspond to particular
display dots and are transferred in sequence, beginning from those corresponding to the
segments of the highest numbers as shown in the enlarged timing diagram in Fig. 2-79. This
operation is repeated on all the SED1120 drives, X1 through X8, to display a single horizontal dot
line. The series of operations needs to be repeated 64 times to display all dotons the entire LCD
panel.
2-77