Epson PX-8 Technical Manual page 63

REV.-A
2.3.2.3 Interrupt
There are only two external interrupt signals to the main CPU; INTR and BURO. The NMI signal is
not used. The main CPU interrupts are discussed in the following.
1. INTR interrupts
The INTR interrupts include the interrupts INTO through INT5 from the sub-CPU 7508, the ser-
ial controller 82C51, the RS-232C interface, the gate array GAH40M, and the option unit.
These interrupts multiplexed by GAH40M and fed to the main CPU as single interrupt request
via the gate array GAH40D (Fig. 2-34).
Main
GAH40D
GAH40D
CPU
(6A) (4C)
(4A)
- -
S-INT
h.
,.,
S-INT
INT3
Sub-CPU 7508
- -
INT4
INTR
h
J"1
Z-INT
r--
~
INTO
RXRDY (SIO 82C52)
- -
P-
INT 1
-
CD (RS-232C interface)
INT2 P-
- -
INT5
h.
INT EX (option unit)
h
Fig. 2-34 INTR Interrupt Request Routing
The two interrupt requests of INT3 (Input Capture flag) and INT4 (Overflow flag) are generated
within GAH40M. All six interrupts are controlled in GAH40M from the main CPU by the corre-
sponding interrupt control bits at I/O address 0004 listed in Table 2-6
Table 2-6 Interrupt Control Bits
Interrupt
Bit name
Interrupt Interrupt
Bit name
Interrupt
control bit vector control bit vector
7 Unused
-
3 IER 3 (lCF) F6
6 Unused
-
2
IER 2 (RS-232C) F4
5 IER 5 (Option unit) FA 1
IER 1 (SID 82C51) F2
4 IER 4 (OVF) F8 0
IER 0 (sub-CPU 7508)
FO
When the INTR signal is generated with the interrupt enabled (i.e., the corresponding IER bit
ON), the main CPU enters the interrupt processing program after the current instruction has
been executed.
2. BURO interrupt
This interrupt request singal is fed from the option unit
0
the main CPU. When it goes low, the
- - -
main CPU forces the address bus, daga bus, and system control terminals (MREO, 10RO, RD,
and WD) in to a high impedance state, making the buses available for use by the option unit
after the current instruction has been executed.
*The interrupt request signals and their function summaries are listed in Table 2-7 in priority
order.
2-39