Device Clock Generation; System Pllc Output Clocks - Texas Instruments AM1808 Technical Reference Manual

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7.2.1 Device Clock Generation

The PLL controllers (PLLC0 and PLLC1) manage the clock ratios, alignment, and gating for the device
system clocks. Various PLL mode attributes such as pre-division, multiplier, and post-division are software
programmable through the PLL controller registers. Additionally, the reset controller in PLLC0 manages
reset propagation through the device, clock alignment, and test points.
The PLLOUT stage in PLLC0 and PLLC1 is capable of providing frequencies greater than what the
SYSCLK dividers can handle. The POSTDIV stage should be programmed to keep the input to the
SYSCLK dividers within operating limits. See the device datasheet for the maximum operating
frequencies.
PLLC0 and PLLC1 generate several clocks for use by the various processors and modules. These
reference clocks are summarized in
clock ratios between various device components are maintained regardless of PLL or bypass frequency.
Output Clock
PLL0_SYSCLK1
PLL0_SYSCLK2
(2)
PLL0_SYSCLK3
PLL0_SYSCLK4
PLL0_SYSCLK5
PLL0_SYSCLK6
PLL0_SYSCLK7
PLL0_AUXCLK
PLL0_OBSCLK
PLL1_SYSCLK1
(3)
PLL1_SYSCLK2
(4)
PLL1_SYSCLK3
(1)
The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.
(2)
PLLC0 supports an additional post-divider value of /4.5 that can be used for EMIFA clock generation. When this /4.5 value is
used, the resulting clock will not have a 50% duty cycle. Instead, the duty cycle will be 44.4%. The EMIFA uses PLL0_SYSCLK3
by default, but can be configured to use a /4.5 divide-down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the
EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG)
module.
(3)
The ASYNC3 modules use PLL0_SYSCLK2 by default, but all these modules can be configured as a group to use
PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system
configuration (SYSCFG) module.
(4)
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit
in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN.
SPRUH82C – April 2013 – Revised September 2016
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Table 7-1. Some output clock dividers require fixed values so that
Table 7-1. System PLLC Output Clocks
Used by
Not used
ARM RAM/ROM, On-chip RAM, UART0,
EDMA, SPI0, MMC/SDs, VPIF, LCDC, SATA,
uPP, DDR2/mDDR (bus ports), USB2.0, HPI,
PRU
EMIFA
System configuration (SYSCFG), GPIO,
PLLCs, PSCs, I2C1, EMAC/MDIO, USB1.1,
ARM INTC
Not used
ARM
EMAC RMII clock
I2C0, Timer64P0/P1, RTC, USB2.0 PHY,
McASP0 serial clock
Observation clock (OBSCLK) source
DDR2/mDDR PHY
ECAPs, UART1/2, Timer64P2/3, eHRPWMs,
McBSPs, McASP0, SPI1 (all these modules
use PLL0_SYSCLK2 by default)
PLL0 input reference clock
(not configured by default)
Copyright © 2013–2016, Texas Instruments Incorporated
Default Ratio
(relative to PLLn_SYSCLK1)
(1)
PLLC0
PLL bypass clock
Pin configurable
PLLC1
/1 or disabled
/2 or disabled
/3 or disabled
Phase-Locked Loop Controller (PLLC)
PLL Controllers
Fixed Clock
Ratio
/1 Yes
/2 Yes
/3 No
/4 Yes
/3 No
/1 Yes
/6 No
No
No
No
No
No
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