Pin Multiplexing And General-Purpose I/O Control Blocks - Texas Instruments AM1808 Technical Reference Manual

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21.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks

Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at
device reset and software programmable register settings. See your device-specific data manual to
determine how pin multiplexing affects the HPI.
The HPI supports general-purpose I/O (GPIO) capability on all pins. All HPI pins may be enabled for GPIO
mode when the HPI is disabled via the HPIENA bit in the chip configuration 1 register (CFGCHIP1) in the
System Configuration (SYSCFG) Module chapter.
When the HPI is enabled, the pins not being used for host accesses may be configured as general-
purpose I/O.
21.2.4.1 Treatment of Optional Pins when Configured as General-Purpose I/O
Certain pins are optional, but if used to interface to the external hosts, the pins are inputs to the HPI. For
the purpose of host accesses, the HPI treats these pins as if they were driven to the values listed in
Table 21-2.
Table 21-2. Value on Optional Pins when Configured as General-Purpose I/O
UHPI_HD[15:8]
UHPI_HD[7:0]
UHPI_HCNTL0
UHPI_HCNTL1
UHPI_HAS
21.2.4.2 General-Purpose I/O Programmer's Model
For each HPI pin, there are three bits that control this pin as general-purpose I/O (GPIO):
• Enable: GPIO_EN.GPIOEN[xx]
• Direction: GPIO_DIRn.DIR[yy]
• Data: GPIO_DATn.DIR[yy]
For example, the UHPI_HAS pin is enabled with the GPIO_EN.GPIOEN2 bit. In the default setting, the
GPIO_EN.GPIOEN2 bit is cleared to 0; therefore, the UHPI_HAS pin functions as the host address strobe.
Enabling this pin for GPIO, by setting the GPIO_EN.GPIOEN2 bit to 1 does two things:
• Transfers control of the UHPI_HAS pin to GPIO direction and data bits.
• Drives a 1 into the UHPI_HAS pin input of the external host interface block (regardless of the actual
pin value).
Once enabled as GPIO, the direction of the UHPI_HAS pin is controlled by the GPIO_DIR2.HASZ bit. If
this bit is set to 1, the pin will be driven as an output; if this bit is cleared to 0, the pin will be an input.
Once the direction of the UHPI_HAS pin is set, the data value is either written to or read from the
GPIO_DAT2.HASZ bit. If the pin was configured as an output, then writing to this bit determines the value
to drive out the pin. Reading from this bit will return the value written.
When the GPIO_DIR2.HASZ bit is cleared to 0, configuring the UHPI_HAS pin as an input, writing to the
GPIO_DAT2.HASZ bit has no effect. Reading from this bit will return the value on the UHPI_HAS pin.
SPRUH82C – April 2013 – Revised September 2016
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Pin GPIO Enable Bit(s)
Copyright © 2013–2016, Texas Instruments Incorporated
When Enabled as GPIO,
Treated as Driven:
GPIOEN8
GPIOEN7
GPIOEN1
GPIOEN1
GPIOEN2
Architecture
0
0
1
1
1
Host Port Interface (HPI)
959