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Architecture
14.2.12 VTP IO Buffer Calibration
The DDR2/mDDR memory controller is able to control the impedance of the output IO. This feature allows
the DDR2/mDDR memory controller to tune the output impedance of the IO to match that of the PCB
board. Control of the output impedance of the IO is an important feature because impedance matching
reduces reflections, creating a cleaner board design. Calibrating the output impedance of the IO will also
reduce the power consumption of the DDR2/mDDR memory controller. The calibration is performed with
respect to voltage, temperature, and process (VTP). The VTP information obtained from the calibration is
used to control the output impedance of the IO.
The impedance of the output IO is selected by the value of a reference resistor connected to pin DDR_ZP.
The DDR2/mDDR reference design requires the reference resistor to be a 50 ohm, 5.0% tolerance, 1/16th
watt resistor (49.9 ohm, 0.5% tolerance is acceptable).
The VTP IO control register (VTPIO_CTL) is written to begin the calibration process. The VTP calibration
process is described in the DDR2/mDDR initialization sequence in
NOTE: VTP IO calibration must be performed following device power up and device reset. If the
DDR2/mDDR memory controller is reset via the Power and Sleep Controller (PSC) and the
VTP input clock is disabled, accesses to the DDR2/mDDR memory controller will not
complete. To re-enable accesses to the DDR2/mDDR memory controller, enable the VTP
input clock and then perform the VTP calibration sequence again.
14.2.13 Auto-Initialization Sequence
The DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on the DDR2/mDDR device), single-ended strobe, differential strobe, etc. The DDR2/mDDR memory
controller programs the mode and extended mode registers of the DDR2/mDDR memory by issuing MRS
and EMRS commands during the initialization sequence. The SDRAMEN, MSDRAMEN, DDREN, and
DDR2EN bits in the SDRAM configuration register (SDCR) determine if the DDR2/mDDR memory
controller will perform a DDR2 or mobile DDR initialization sequence. Set these bits as follows for DDR2:
SDRAMEN = 1, MSDRAMEN = 0, DDREN = 1, DDR2EN = 1. Set these bits as follow for mDDR:
SDRAMEN = 1, MSDRAMEN = 1, DDREN = 1, DDR2EN = 0. The DDR2 initialization sequence
performed by the DDR2/mDDR memory controller is compliant with the JESD79D-2 specification and the
mDDR initialization sequence is compliant with the JESD209 specification. The DDR2/mDDR memory
controller performs an initialization sequence under the following conditions:
•
Following reset (rising edge of chip_rst_n or mod_g_rst_n)
•
Following a write to the DDRDRIVE, CL, IBANK, or PAGESIZE bit fields in the SDRAM configuration
register (SDCR)
During the initialization sequence, the memory controller issues MRS and EMRS commands that
configure the DDR2/mobile DDR SDRAM mode register and extended mode register 1. The register
values for DDR2 are described in
described in
Table 14-13
value of 0h. At the end of the initialization sequence, the memory controller performs an autorefresh cycle,
leaving the memory controller in an idle state with all banks deactivated.
When a reset occurs, the DDR2/mDDR memory controller immediately begins the initialization sequence.
Under this condition, commands and data stored in the DDR2/mDDR memory controller FIFOs will be lost.
However, when the initialization sequence is initiated by a write to the two least-significant bytes in SDCR,
data and commands stored in the DDR2/mDDR memory controller FIFOs will not be lost and the
DDR2/mDDR memory controller will ensure read and write commands are completed before starting the
initialization sequence.
392
DDR2/mDDR Memory Controller
Table 14-11
and
and
Table
14-14. The extended mode registers 2 and 3 are configured with a
Copyright © 2013–2016, Texas Instruments Incorporated
Section
14.2.13.1.
Table
14-12, and the register values for mDDR are
SPRUH82C – April 2013 – Revised September 2016
www.ti.com
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