Texas Instruments AM62A7 Hardware Design Manual

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Application Note
Hardware Design Guide for AM62A7/AM62A3 Devices
This hardware design guide gives an overview of the design considerations to be followed by the board
designers using AM62A7/AM62A3 family of processors. This application note is intended to be used at different
stages of board design as a guide by the designers. The hardware design guide additionally references to
collaterals (device-specific and common) that could help the designers to optimize the efforts during the board
design.
1 Introduction.............................................................................................................................................................................2
1.1 Before Getting Started.......................................................................................................................................................
1.2 Device (Processor) Selection.............................................................................................................................................2
1.3 Technical Documentation...................................................................................................................................................
1.4 Design Documentation.......................................................................................................................................................3
2 System Block Diagram...........................................................................................................................................................3
2.1 Creating the System Block Diagram..................................................................................................................................
2.2 Selecting the Boot Mode....................................................................................................................................................
2.3 Confirming Pin Multiplexing Compatibility..........................................................................................................................
3 Power Supply..........................................................................................................................................................................
3.1 Power Supply Architecture.................................................................................................................................................4
3.2 Power (Supply) Rails..........................................................................................................................................................4
3.3 Determining System Power Requirements........................................................................................................................
3.4 Power Supply Filters..........................................................................................................................................................
3.5 Power Supply Decoupling and Bulk
3.6 Power Supply Sequencing.................................................................................................................................................
3.7 Supply Diagnostics.............................................................................................................................................................6
3.8 Power Supply Monitoring...................................................................................................................................................
4 Clocking...................................................................................................................................................................................7
4.1 System Clock Inputs..........................................................................................................................................................
4.2 Unused Clock Inputs..........................................................................................................................................................
4.3 Clock Output......................................................................................................................................................................
4.4 Single-Ended Clock Sources.............................................................................................................................................
4.5 Crystal Selection................................................................................................................................................................
5 JTAG.........................................................................................................................................................................................7
5.1 JTAG / Emulation...............................................................................................................................................................
6 Device Configurations and
6.1 Device Reset......................................................................................................................................................................8
6.2 Latching of the Boot Modes...............................................................................................................................................
6.3 Watchdog Timer.................................................................................................................................................................
7 Peripherals..............................................................................................................................................................................
7.1 Selecting Peripherals Across Functional Domains............................................................................................................
7.2 Memory..............................................................................................................................................................................
7.3 Media and Data Storage Interfaces.................................................................................................................................
7.4 Ethernet Interface Using CPSW3G Common Platform Switch 3-port Gigabit
7.5 Programmable Real-Time Unit Subsystem (PRUSS)......................................................................................................
7.6 Universal Serial Bus (USB) Subsystem...........................................................................................................................
7.7 General Connectivity........................................................................................................................................................10
7.8 Display Subsystem (DSS)................................................................................................................................................
7.9 Camera Subsystem (CSI).................................................................................................................................................11
7.10 Termination of Unused Peripherals and
8 I/O Buffers and Termination.................................................................................................................................................
SPRAD85 - MARCH 2023
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ABSTRACT

Table of Contents

Capacitors.................................................................................................................6
Initialization...............................................................................................................................8
I/Os..................................................................................................................11
Copyright © 2023 Texas Instruments Incorporated
Ethernet...................................................10
Hardware Design Guide for AM62A7/AM62A3 Devices
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