Architecture; Clock Control; Ddr2/Mddr Memory Controller Clock Block Diagram - Texas Instruments AM1808 Technical Reference Manual

Architecture

14.2 Architecture
This section describes the architecture of the DDR2/mDDR memory controller as well as how it is
structured and how it works within the context of the system-on-a-chip. The DDR2/mDDR memory
controller can gluelessly interface to most standard DDR2/mDDR SDRAM devices and supports such
features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through
programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
The following sections include details on how to interface and properly configure the DDR2/mDDR
memory controller to perform read and write operations to externally-connected DDR2/mDDR SDRAM
devices. Also, Section 14.3
to a common DDR2/mDDR SDRAM device.

14.2.1 Clock Control

The DDR2/mDDR memory controller receives two input clocks from internal clock sources, VCLK and
2X_CLK (Figure 14-2). VCLK is a divided-down version of the PLL0 clock. 2X_CLK is the PLL1 clock.
2X_CLK should be configured to clock at the frequency of the desired data rate, or stated similarly, it
should operate at twice the frequency of the desired DDR2/mDDR memory clock. DDR_CLK and
DDR_CLK are the two output clocks of the DDR2/mDDR memory controller providing the interface clock
to the DDR2/mDDR SDRAM memory. These two clocks operate at a frequency of 2X_CLK/2.
14.2.1.1 Clock Source
VCLK and 2X_CLK are sourced from two independent PLLs
controller 0 (PLLC0) and 2X_CLK is sourced from PLL controller 1 (PLLC1).
VCLK is clocked at a fixed divider ratio of PLL0. This divider is fixed at 2, meaning VCLK is clocked at a
frequency of PLL0/2.
The clock from PLLC1 is not divided before reaching 2X_CLK. PLLC1 should be configured to supply
2X_CLK at the desired frequency. For example, if a 138-MHz DDR2/mDDR interface clock (DDR_CLK) is
desired, then PLLC1 must be configured to generate a 276-MHz clock on 2X_CLK.
Figure 14-2. DDR2/mDDR Memory Controller Clock Block Diagram
370
DDR2/mDDR Memory Controller
provides a detailed example of interfacing the DDR2/mDDR memory controller
DDR_CLK DDR_CLK
DDR2
memory
controller
VCLK
/2
PLLC0
Copyright © 2013–2016, Texas Instruments Incorporated
(Figure 14-2). VCLK is sourced from PLL
2X_CLK
/1
PLLC1
SPRUH82C – April 2013 – Revised September 2016
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