256-Entry Palette/Buffer Format (8 Bpp); 16-Bpp Data Memory Organization (Tft Mode Only)-Little Endian - Texas Instruments AM1808 Technical Reference Manual

Architecture
Bit 15 14
Color Unused
Bit 15 14
Mono Unused
A. Bits-per-pixels (BPP) is only contained within the first palette entry (palette entry 0).
Bits 12, 13, and 14 of the first palette entry select the number of bits-per-pixel to be used in the following
frame and thus the number of palette RAM entries. The palette entry is used by the Raster Controller to
correctly unpack pixel data.
The following figures show the memory organization within the frame buffer for each pixel encoding size.
Figure 23-7. 16-BPP Data Memory Organization (TFT Mode Only)—Little Endian
Bit 15
16 bits/pixel
1040
Liquid Crystal Display Controller (LCDC)
Figure 23-6. 256-Entry Palette/Buffer Format (8 BPP)
Individual Palette Entry
13 12 11 10
(A)
BPP Red (R)
13 12 11 10
(A)
BPP
Bit
Base + 0
Base + 2
Base + FCh
Base + FEh
14 13 12 11 10
R
Base + 2
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9 8 7 6 5
Green (G)
9 8 7 6 5
Unused
256-Entry Palette Buffer
15
Palette Entry 0
Palette Entry 1
.
.
.
Palette Entry 254
Palette Entry 255
9 8 7 6 5
G
Bit 15
Base
SPRUH82C – April 2013 – Revised September 2016
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4 3 2 1 0
Blue (B)
4 3 2 1 0
Mono (M)
0
.
.
.
4 3 2 1 0
B
0
Pixel 0
Pixel 1
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