Spi Registers; Programmable Registers - Texas Instruments AM1808 Technical Reference Manual

Architecture

29.2.4 Programmable Registers

A general representation of the SPI programmable registers is shown in
registers, see Section
Offset
(1)
Address Acronym
0h SPIGCR0
4h SPIGCR1
8h SPIINT0
Ch SPILVL
10h SPIFLG
14h SPIPC0
18h SPIPC1
1Ch SPIPC2
20h SPIPC3
24h SPIPC4
28h SPIPC5
38h SPIDAT0
3Ch SPIDAT1
40h SPIBUF
44h SPIEMU
48h SPIDELAY
4Ch SPIDEF
50h SPIFMT0
54h SPIFMT1
58h SPIFMT2
5Ch SPIFMT3
64h INTVEC1
(1)
The actual address of these registers is device specific and CPU specific. See your device-specific data manual to verify the SPI
register addresses.
1416
Serial Peripheral Interface (SPI)
29.3.
Table 29-2. SPI Registers
Name
Global control register 0
Global control register 1
Interrupt register
Level register
Flag register
Pin control register 0
Pin control register 1
Pin control register 2
Pin control register 3
Pin control register 4
Pin control register 5
Transmit data register 0
Transmit data register 1
Receive buffer register
Receive buffer emulation
register
Delay register
Chip select default register In SPIx_SCS[n] decoded mode only:
Format 0 register
Format 1 register
Format 2 register
Format 3 register
Interrupt vector register 1
Copyright © 2013–2016, Texas Instruments Incorporated
Table
Description
Contains the software reset bit for the
module
Controls basic configurations of the
module
Enable bits for interrupts, error, DMA
and other functionality.
SPI interrupt levels are set in this
register.
Shows the status of several events
during the operation.
Determines if pins operate as general
I/O or SPI functional pin
Controls the direction of data on the I/O
pins
Reflects the values on the I/O pins
Controls the values sent to the I/O pins
Sets data values in the SPIPC3 register
Clears values in the SPIPC3 register
Transmit data register
Transmit data with format selection
register
Holds received word
Mirror of SPIBUF. Read does not clear
flags
Sets SPIx_SCS[n] mode, SPIx_SCS[n]
pre-/post-transfer delay time and
SPIx_ENA time-out
sets high low/active SPIx_SCS[n] signal
Configuration of data word format 0
Configuration of data word format 1
Configuration of data word format 2
Configuration of data word format 3
Interrupt vector for line INT1
SPRUH82C – April 2013 – Revised September 2016
www.ti.com
29-2. For details on
Section
Section 29.3.1
Section 29.3.2
Section 29.3.3
Section 29.3.4
Section 29.3.5
Section 29.3.6
Section 29.3.7
Section 29.3.8
Section 29.3.9
Section 29.3.10
Section 29.3.11
Section 29.3.12
Section 29.3.13
Section 29.3.14
Section 29.3.15
Section 29.3.16
Section 29.3.17
Section 29.3.18
Section 29.3.18
Section 29.3.18
Section 29.3.18
Section 29.3.19
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