Phb Hardware Configuration; Table 2-15. Phb Hardware Configuration - Motorola MVME5100 Programmer's Reference Manual

The PCI Slave decode logic settles out several clocks after the assertion of
FRAME_, at which time the PCI Slave can determine the transaction type.
If it is a read and PFBR is enabled, the PCI Slave will look at the xs_fbrabt
signal. If this signal is active, the PCI Slave will retry the PCI Master.

PHB Hardware Configuration

Hawk has the ability to perform custom hardware configuration to
accommodate different system requirements. The PHB has several
functions that may be optionally enabled or disabled using passive
hardware external to Hawk. The selection process occurs at the first rising
edge of CLK after RST_ has been released. All of the sampled pins are
cascaded with several layers of registers to eliminate problems with hold
time.
Table 2-15
the PHB.

Table 2-15. PHB Hardware Configuration

Function
PCI 64-bit Enable
PPC Register Base
MPIC Interrupt Type
PPC Arbiter Mode
PCI Arbiter Mode
http://www.motorola.com/computer/literature
summarizes the hardware configuration options that relate to
Sample Pin(s) Sampled
State
REQ64_
RD[5]
RD[7]
RD[8]
RD[9]
Functional Description
Meaning
0 64-bit PCI Bus
1 32-bit PCI Bus
0 Register Base = $FEFF0000
1 Register Base = $FEFE0000
0 Parallel Interrupts
1 Serial Interrupts
0 Disabled
1 Enabled
0 Disabled
1 Enabled
2
2-49