Rom B Base/Size Register - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)

ROM B Base/Size Register

Address
Bit
3
Name
Operation
Reset
3-56
ROM B BASE
READ/WRITE
$FF4 PL
Writes to this register must be enveloped by a period of time in which no
accesses to ROM/Flash Block B, occur. A simple way to provide the
envelope is to perform at least two accesses to this (or another of the
SMC's registers before and after the write).
ROM B BASE These control bits define the base address for ROM/Flash
Block B. ROM B BASE bits 0-11 correspond to PPC60x
address bits 0 - 11 respectively. For larger ROM/Flash
sizes, the lower significant bits of ROM B BASE are
ignored. This means that the block's base address will
always appear at an even multiple of its size. ROM B
BASE is initialized to $FF4 at power-up or local bus reset.
Note that in addition to the programmed address, the first
1Mbyte of Block B also appears at $FFF00000 -
$FFFFFFFF if the rom_b_rv bit is set.
Also note that the combination of ROM_B_BASE and
rom_b_siz should never be programmed such that
ROM/Flash Block B responds at the same address as the
CSR, SDRAM, External Register Set, or any other slave
on the PowerPC bus.
$FEF80058
READ ZERO
X
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